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1 for more information www.linear.com/ltc3766 typical a pplica t ion fea t ures descrip t ion high efficiency, secondary-side synchronous forward controller the lt c ? 3766 is a polyphase-capable secondary-side controller for synchronous forward converters. when used in conjunction with the ltc3765 active-clamp forward controller and gate driver, the part creates a complete isolated power supply that combines the power of multi - phase operation with the speed of secondary-side control. the l tc3766 has been designed to simplify the design of active clamp for ward converters. working in concert with the ltc3765, the ltc3766 forms a robust, self-starting converter that eliminates the need for the separate bias regulator that is commonly used in secondary-side control applications. a precision current-limit coupled with clean start-up into a pre-biased load make the ltc3766 an excel - lent choice for high-power battery charger applications. t h e ltc3766 provides extensive remote sensing and output protection features, while direct flux limit guarantees no transformer saturation without compromising transient response. a linear regulator controller and internal bypass ldo are also provided to simplify the generation of the secondary-side bias voltage. 36v-72v to 5v/15a active clamp isolated forward converter a pplica t ions n direct flux limit? guarantees no saturation n fast and accurate average current limit n clean start-up into pre-biased output n secondary-side control for fast transient response n simple, self-starting architecture n synchronous mosfet reverse current limit n polyphase ? operation eases high-power design n true remote sense differential amplifier n remote sense reverse protection n high voltage linear regulator controller n internal ldo powers gate drive from v out n overtemperature/overvoltage protection n low profile 4mm 5mm qfn and narrow 28-lead ssop packages n isolated 48v telecommunication systems n isolated battery chargers n automotive and military systems n industrial, avionics and heavy equipment l , lt, ltc, ltm, polyphase, linear technology and the linear logo are registered and direct flux limit is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents, including 7200014 and 6144194. other patents pending. fg i s ? i s + pt + fb ith pt ? ss sw sg gnd pgnd sgd fgd mode run v in ndrv ltc3766 v cc run si3437dv (sot23) 15m 0.5w 3m 2w v cc in + in ? fs/uv ssflt ndrv pg r core delay sgnd 14k 18.2k efficiency: 94% at 48v in /15a out 15k 26.1k 33nf 22.1k 17.8k 3766 ta01 604 4.42k 0.1f 2:1 6:2 10.5k 15.0k 365k i pk 200k si3440dv ?v in +v in 36v to 72v fdms86201 bsc0901ns ?? sir414dp 33nf 4.7f ltc3765 pgnd i s + i s ? ag 1 168 i smag fs/sync v s + v s ? 1.0f 2.2nf 250vac 33nf 200v 47pf 470pf 2.2f 100v 3 220f 6.3v 2 1.4h +v out 5v 15a ?v out 100nf 200v ? ? ltc3766 3766fa
2 for more information www.linear.com/ltc3766 a bsolu t e maxi m u m r a t ings v cc voltage ................................................. C 0.3v to 12v v in voltage ................................................. C 0.3v to 33v run voltage ............................................... C0.3v to 33v sw lo w impedance source ............................ C 5v to 40v cu rrent fed .......... 2 ma dc or 0.2a for <1s into pin* v aux , v s + , v s C , v sout , ndrv voltages ...... C0 .3v to 16v ith, i s + , regsd voltages ............................ C0 .3v to 6v phase voltage ............................................. C 0.3v to 6v i s C , sgd, fgd voltages ............................... C0 .3v to 12v fs/sync, fb, mode voltages ..................... C 0.3v to 12v (note 1) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 top view gn package 28-lead narrow plastic ssop 28 27 26 25 24 23 22 21 20 19 18 17 16 15 sg fg v sec mode phase fb ith run ss i pk v sout v s + v s ? gnd v cc pgnd pt + pt ? v aux sw v in ndrv fgd sgd i s + i s ? regsd fs/sync t jmax = 125c, ja = 95c/w 9 10 top view 29 gnd ufd package 28-lead (4mm 5mm) plastic qfn 11 12 13 28 27 26 25 24 14 23 6 5 4 3 2 1 mode phase fb ith run ss i pk v sout pt ? v aux sw v in ndrv fgd sgd i s + v sec fg sg v cc pgnd pt + v s + v s ? gnd fs/sync regsd i s ? 7 17 18 19 20 21 22 16 8 15 t jmax = 125c, ja = 43c/w exposed pad (pin 29) is gnd, must be soldered to pcb p in c on f igura t ion v sec voltage ................................................ C 0.3v to 3v i pk , ss voltages ........................................... C0 .3v to 4v operating junction temperature range (notes 2,3) ltc 3766e, ltc3766i ......................... C 40c to 125c lt c3766h .......................................... C 40c to 150c lt c3766mp ....................................... C 55c to 150c storage temperature range .................. C 65c to 150c lead temperature (soldering, 10 sec ) gn p ackage ..................................................... 3 00c *the ltc3766 contains an internal 50v clamp that limits the voltage on the sw pin. ltc3766 3766fa
3 for more information www.linear.com/ltc3766 e lec t rical c harac t eris t ics the l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at t a = 25c. (note 2) v in = 15v, gnd = pgnd = 0v, unless otherwise noted. o r d er i n f or m a t ion lead free finish tape and reel part marking* package description temperature range ltc3766egn#pbf ltc3766egn#trpbf ltc3766gn 28-lead narrow plastic ssop C40c to 125c ltc3766ign#pbf ltc3766ign#trpbf ltc3766gn 28-lead narrow plastic ssop C40c to 125c ltc3766hgn#pbf ltc3766hgn#trpbf ltc3766gn 28-lead narrow plastic ssop C40c to 150c ltc3766mpgn#pbf ltc3766mpgn#trpbf ltc3766gn 28-lead narrow plastic ssop C55c to 150c ltc3766eufd#pbf ltc3766eufd#trpbf 3766 28-lead (4mm 5mm) plastic qfn C40c to 125c ltc3766iufd#pbf ltc3766iufd#trpbf 3766 28-lead (4mm 5mm) plastic qfn C40c to 125c ltc3766hufd#pbf ltc3766hufd#trpbf 3766 28-lead (4mm 5mm) plastic qfn C40c to 150c ltc3766mpufd#pbf ltc3766mpufd#trpbf 3766 28-lead (4mm 5mm) plastic qfn C55c to 150c consult ltc marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. consult ltc marketing for information on non-standard lead based finish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ symbol parameter conditions min typ max units main control loop v fb regulated feedback voltage (note 4) ith = 1.2v l 0.592 0.600 0.608 v i fb feedback input current (note 4) 2 50 na v fb(linreg) feedback voltage line regulation v in = 5v to 32v, ith = 1.2v 0.001 %/v v fb(loadreg) feedback voltage load regulation measured in servo loop, ith = 0.5v to 2v l C0.01 C0.1 % v isavg average current sense threshold resistor sense (rs) mode current transformer (ct) mode 47 0.66 55 0.73 63 0.80 mv v v isadj current sense ripple compensation rs mode ct mode v sw = 10v, v s + = 5v, fs/sync = v cc , r ipk = 23.7k 10 140 mv mv v isoc overcurrent shutdown threshold rs mode: v is C = 0v ct mode: v is C = v cc 86 1.22 100 1.33 113 1.44 mv v i sin i s + and i s C input current 280 500 na g m error amplifier g m 2.2 2.7 3.2 ms r ea error amplifier output resistance (note 7) 5 m i soft(c) soft-start charge current v ss = 2v 4 5 6 a i soft(d) soft-start discharge current v ss = 2v 3 a v runr run pin on threshold v run rising l 1.18 1.22 1.26 v v runf run pin off threshold v run falling l 1.13 1.17 1.21 v i run run pin hysteresis current v run = 0.5v 2.2 3.0 3.6 a t on(min) minimum controllable on time 200 ns d max maximum duty cycle fgd = sgd = gnd 77 79 81 % v sec(th) volt-second limit threshold accuracy 2v v sw < 5v 5v v sw 40v C6 C4 6 4 % % r vsdn volt-second discharge resistance 75 v swcl sw clamp voltage i sw = 1ma 43 51 60 v v fb(ov) output overvoltage threshold v fb rising 15 17 19 % ltc3766 3766fa
4 for more information www.linear.com/ltc3766 e lec t rical c harac t eris t ics the l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at t a = 25c. (note 2) v in = 15v, gnd = pgnd = 0v, unless otherwise noted. symbol parameter conditions min typ max units drivers and control fg, sg r up fg, sg driver pull-up on-resistance 1.5 fg, sg r down fg, sg driver pull-down on-resistance 1.0 pt + , pt C r up pt + , pt C driver pull-up resistance 1.5 pt + ,pt C r down pt + , pt C driver pull-down resistance 1.5 t fgd fgd delay r fgd = 10k r fgd = 100k 50 436 65 545 80 654 ns ns t sgd sgd delay r sgd = 15k r sgd = 50k 60 195 75 230 90 265 ns ns v sw(rev) sg reverse overcurrent sw threshold lv mode hv mode 66 140 73 148 79 156 mv mv i sw(rev) sg reverse overcurrent adjust current lv mode hv mode C86 C34.5 C103 C42 C120 C49 a a v cc supply v ccop v cc operating voltage range 5 10 v i cc supply current normal mode shutdown v fs/sync = v cc = 7v (note 5) v run = gnd 5 210 ma a v uvlor uv lockout rising v cc rising, lv mode v cc rising, hv mode l l 4.6 7.7 4.7 7.9 4.8 8.1 v v v uvlof uv lockout falling v cc falling, lv mode v cc falling, hv mode l l 3.8 6.7 3.9 6.9 4.0 7.1 v v v regsd regsd threshold voltage v regsd rising 1.21 v i regsd(c) regsd charge current v regsd = 0.7v 13 a i regsd(d) regsd discharge current v regsd = 0.7v 3 a v aux supply v auxop v aux operating voltage range 5 15 v v ccvaux regulated v cc output voltage v aux = 15v, lv mode v aux = 15v, hv mode 6.7 8.1 7.0 8.5 7.3 8.9 v v v auxlr v cc load regulation i cc = 0ma to 120ma, v aux = 8v, lv mode 0.8 2 % v auxswp v aux switchover voltage rising v aux ramping positive, lv mode v aux ramping positive, hv mode 4.50 7.65 4.70 8.00 4.88 8.35 v v v auxswn v aux switchover voltage falling v aux ramping negative, lv mode v aux ramping negative, hv mode 4.30 7.35 4.50 7.70 4.70 8.05 v v r aux v aux dropout resistance i cc = 120ma, v aux = 4.9v 1.7 2.5 r psl v aux pre-switchover load v aux = 4v 920 v in supply v inop v in operating voltage range 5 32 v v incl v in clamp voltage i vin = 2ma, v run = gnd 28 30 32 v i clmax v in clamp current limit v in = 33v, v run = gnd 3.8 5.5 7.2 ma v ccvin regulated v cc output voltage lv mode (note 6) hv mode (note 6) 6.7 8.1 7.2 8.5 7.3 8.9 v v i in supply current operating shutdown v fs/sync = v cc v run = gnd 900 450 1200 a a v inuvlo v in undervoltage lockout v in rising 2.6 3.2 3.8 v ltc3766 3766fa
5 for more information www.linear.com/ltc3766 e lec t rical c harac t eris t ics the l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at t a = 25c. (note 2) v in = 15v, gnd = pgnd = 0v, unless otherwise noted. symbol parameter conditions min typ max units oscillator and phase-locked loop i fs/sync fs/sync pin sourcing current 20 a f high oscillator high frequency set point v fs/sync = v cc 234 275 316 khz f (r fs/sync ) oscillator resistor set accuracy 18.75k < r fs/sync < 125k l C12 12 % f pll(range) pll sync frequency range 100 500 khz differential amplifier a da gain 1.5v v sout 15v, v in = 20v 0.99 1 1.01 v/v cmrr da common mode rejection ratio v in = 20v 75 db r inp v s + input resistance v in = 20v 120 k r inm v s C input resistance v in = 20v 160 k i oh output sourcing current v in = 20v, v s + = 5v, v sout = 2.5v l 0.8 3.0 ma v in -v ohst output high fault threshold v s + rising 1.2 1.5 v note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the ltc3766e is guaranteed to meet specifications from 0c to 85c with specifications over the C40c to 125c operating junction temperature range assured by design, characterization and correlation with statistical process controls. the ltc3766i is guaranteed over the C40c to 125c operating junction temperature range, the ltc3766h is guaranteed over the C40c to 150c operating junction temperature range, and the ltc3766mp is tested and guaranteed over the C55c to 150c operating junction temperature range. high junction temperatures degrade operating lifetimes; operating lifetime is derated for junction temperatures greater than 125c. note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal impedance and other environmental factors. note 3: t j is calculated from the ambient temperature, t a , and power dissipation, p d , according to the following formula: t j = t a + (p d ? ja c/w) where ja is 95c/w for the ssop and 43c/w for the qfn package. note 4: the ltc3766 is tested in a feedback loop that servos v fb to a voltage near the internal 0.6v reference voltage to obtain the specified ith voltage (v ith = 1.2v). note 5: operating supply current is measured in test mode. dynamic supply current is higher due to the internal gate charge being delivered at the switching frequency. see typical performance characteristics. note 6: the v in regulator employs an external pass device to produce the regulated v cc output voltage. the ltc3766 is tested using a 2n3904 npn transistor as an external pass device. note 7: guaranteed by design. ltc3766 3766fa
6 for more information www.linear.com/ltc3766 typical p er f or m ance c harac t eris t ics overcurrent shutdown threshold vs temperature v aux drop-out resistance vs temperature average current sense threshold vs temperature run threshold vs temperature run hysteresis current vs temperature oscillator frequency vs r fs v cc supply current vs v cc voltage v cc regulator output voltage vs temperature error amplifier transconductance vs temperature v cc input voltage (v) 5 11 12 14 8 10 3766 g01 10 9 6 7 9 11 12 8 7 13 v cc supply current (ma) temperature (c) ?55 v cc voltage (v) 8.0 8.5 9.0 35 95 3766 g02 7.5 7.0 ?25 5 65 125 155 6.5 6.0 v in regulator using 2n3904 hv mode lv mode temperature (c) ?55 2.70 transconductance (ms) 2.75 2.80 2.85 2.90 ?25 5 35 65 3766 g03 95 125 155 temperature (c) ?55 ct mode threshold (v) rs mode threshold (mv) 1.330 1.335 1.340 35 95 3766 g04 1.325 1.320 ?25 5 65 125 155 1.315 1.310 101 102 103 100 99 98 97 ct mode rs mode temperature (c) ?55 resistance () 2.0 2.5 3.0 35 95 3766 g05 1.5 1.0 ?25 5 65 125 155 0.5 0 temperature (c) ?55 ct mode threshold (v) rs mode threshold (mv) 0.740 0.745 0.750 35 95 3766 g04 0.735 0.730 ?25 5 65 125 155 0.725 0.720 55.0 55.5 56.0 54.5 54.0 53.5 53.0 rs mode ct mode temperature (c) ?55 run voltage (v) 1.220 1.222 1.224 35 95 3766 g07 1.218 1.216 ?25 5 65 125 155 1.214 1.212 run voltage rising temperature (c) ?55 run current (a) 3.00 3.05 3.10 35 95 3766 g08 2.95 2.90 ?25 5 65 125 155 2.85 2.80 v run = 0.5v r fs (k) 0 frequency (khz) 400 500 600 75 125 3766 g09 300 200 25 50 100 150 0 100 ltc3766 3766fa
7 for more information www.linear.com/ltc3766 typical p er f or m ance c harac t eris t ics fgd delay vs resistance sgd delay vs temperature fgd delay vs temperature gate driver on-resistance vs v cc voltage efficiency (figure 39 circuit) load step (figure 39 circuit) oscillator frequency vs temperature fb voltage vs temperature sgd delay vs resistance temperature (c) ?55 change in frequency (%) 1.0 1.5 2.0 35 95 3766 g10 0.5 0 ?25 5 65 125 155 ?0.5 ?1.0 fs = 18.7k fs = 124k fs = v cc temperarture (c) ?55 598.0 v fb (mv) 598.2 598.6 598.8 599.0 65 599.8 3766 g11 598.4 5 ?25 95 125 35 155 599.2 599.4 599.6 r sgd (k) 0 delay (ns) 150 200 250 40 3766 g12 100 50 0 10 20 30 50 sg rising fg falling mode = 100k to gnd sw tied to pt + r fgd (k) 0 700 600 500 400 300 200 100 0 60 100 3766 g13 20 40 80 120 delay (ns) temperature (c) ?55 ?25 0 delay (ns) 100 250 5 65 95 3766 g14 50 200 150 35 125 155 r sgd = 49.9k r sgd = 15k temperature (c) ?55 delay (ns) 400 500 600 35 95 3766 g15 300 200 ?25 5 65 125 155 100 0 r fgd = 100k r fgd = 10k v cc voltage (v) 5 1.50 1.75 2.25 8 10 3766 g16 1.25 1.00 6 7 9 11 12 0.75 0.50 2.00 resistance () pt + , pt ? pull-down fg,sg pull-down all gates pull-up load current (a) 3 86 efficiency (%) 88 90 92 94 96 5 7 9 11 3766 g17 13 15 v in = 36v v in = 48v v in = 72v v out 200mv/div i out 5a/div 20s/div 3766 g18 v in = 48v v out = 5v load step = 5a to 15a ltc3766 3766fa
8 for more information www.linear.com/ltc3766 p in func t ions (ssop/qfn) sg (pin 1/pin 26): gate drive for the synchronous mosfet. fg (pin 2/pin 27): gate drive for the forward mosfet. v sec (pin 3/pin 28): volt-second limit. connect a resistor from sw to v sec , and a capacitor from v sec to gnd to set the maximum volt-second product that is applied to the main power transformer. the pwm on-time is terminated when the v sec voltage exceeds the internally generated threshold. tie to gnd if not used. mode (pin 4/pin 1): for normal isolated applications using the ltc3765, tie to either gnd or v cc to set the operating voltage to either low voltage or high voltage modes respectively, as needed to drive the gates of the synchronous and forward mosfets. for nonisolated applications, tie to ground through either a 100k or 50k resistor to activate standalone mode (for low voltage or high voltage operation respectively). in this mode, the pt + pin may be directly connected to the gate of a primary-side mosfet, and a reference clock signal is generated on the pt C pin. in standalone mode, the fgd pin is ignored and the associated delay is set adaptively. phase (pin 5/pin 2): control input to the phase selector. this pin determines the phasing of the internal controller clk relative to the synchronizing signal at the fs/sync pin. fb (pin 6/pin 3): the inverting input of the main loop error amplifier. tie to v cc to enable slave mode in polyphase applications. ith (pin 7/pin 4): the output of the main loop error amplifier . place compensation components between the ith pin and gnd. run (pin 8/pin 5): run control input. holding this pin below 1.22v will shut down the ic and reset the soft-start and regsd pins to 0v. ss (pin 9/pin 6): soft-start inputs. a capacitor to ground sets the ramp time of the output voltage. i pk (pin 10/pin 7): peak current limit inductor ripple cancellation. this pin is used to adjust the peak current limit based on the amount of inductor current ripple, thereby providing a constant average output current during current limit. place a resistor to gnd that is proportional to the main output inductor. leave this pin floating for constant peak current limit. minimize parasitic capacitance on this pin. v sout , v s + , v s C (pins 11, 12, 13/pins 8, 9, 10): v sout is the output of a precision, unity-gain differential amplifier. tie v s + and v s C to the output of the main dc/dc converter to achieve true remote differential sensing. also, v s + is used for directly sensing the output voltage for inductor ripple cancellation. see the applications information sec - tion for details. gnd (pin 14/pin 11, exposed pad pin 29): signal ground and kelvin sense for sg reverse over current. connect to power ground at the source of the synchronous mosfet. the exposed pad must be soldered to pcb ground for rated thermal performance. fs/sync (pin 15/pin 12): combination frequency set and sync pin. tie to v cc to run at 275khz. place a resistor to ground at this pin to set the frequency between 75khz and 500khz. to synchronize, drive this pin with a clock signal to achieve pll synchronization from 100khz to 500khz. sources 20a of current. regsd (pin 16/pin 13): regulator shutdown timer. place a capacitor to ground to limit the time allowed for the high voltage linear regulator controller to operate. when the regsd voltage exceeds 1.21v, the linear regulator is shut down. this pin sources 13a of current when the linear regulator is active. i s C (pin 17/pin 14): negative input to the current sense circuit. connect to the negative end of a low side current sense resistor. when using a current sense transformer, tie this pin to v cc for single-ended sensing on i s + with a higher maximum trip level. i s + (pin 18/pin 15): positive input to the current sense circuit. connect to the positive end of a low side cur - rent sense resistor or to the output of a current sense tr a nsformer. sgd (pin 19/pin 16): synchronous gate rising edge delay. a resistor to gnd sets the delay from primary gate turn- off (pt + falling) to sg rising (and fg falling). this delay is used to optimize the dead time between the turn-off of the primary-side mosfet and the turn-on of sg. tie sgd to gnd to set this delay adaptively based on the falling edge of the sw pin voltage. see setting the gate driver delays in the applications information section. ltc3766 3766fa
9 for more information www.linear.com/ltc3766 p in func t ions (ssop/qfn) fgd (pin 20/pin 17): forward gate rising edge delay. a resistor to gnd sets the delay from pt + rising to fg rising (and sg falling). this delay is used to optimize the dead time between the turn-off of sg and the turn-on of the primary-side mosfet. in standalone mode (100k or 50k resistor on mode), this dead time is set adaptively and the fgd pin can be grounded. see setting the gate driver delays in the applications information section. ndrv (pin 21/pin 18): drive output for the external pass device of the high voltage linear regulator controller. connect to the base (npn) or gate (mosfet) of an exter - nal n-type device. tie to v cc pin if only using the internal ldo (v aux pin). v in (pin 22/pin 19): connect to a higher voltage bias supply when using the linear regulator controller. the v in pin supplies bias to the internal standby and monitoring circuits, the linear regulator controller, and the differential amplifier. tie to v aux pin if only using the internal ldo. sw (pin 23/pin 20): connect (kelvin) to the drain of the synchronous mosfet. this input is used for adaptive shoot-through prevention and leading-edge blanking, monitoring the high level sw node voltage and sg reverse- current protection. when sw is high, the voltage on this pin is internally measured for use in the inductor ripple cancellation and volt-second limit circuits. when sw is low and sg is high, this pin sources a small current and is used for sg reverse overcurrent protection. a resistor can be placed between the sw pin and the drain of the synchronous mosfet to adjust the sg reverse-overcurrent threshold. the sw pin is internally clamped to 50v. v aux (pin 24/pin 21): auxiliary power input. this is the power input to an internal ldo that is connected to v cc . whenever v aux is greater than 4.7v (or 8v for high voltage mode), this ldo will supply power to v cc , bypassing the main linear regulator that is powered from v in . see v aux connection in the applications information section. do not exceed 16v on the v aux pin. pt C , pt + (pin 25, 26/pin 22, 23): pulse transformer driver outputs. for most applications, these connect to a pulse transformer through a series dc-blocking capacitor. the pwm information is multiplexed together with dc power and sent through the pulse transformer to the primary side. the pwm signal is then decoded by the ltc3765 active clamp forward controller and gate driver. in standalone mode (100k or 50k resistor on mode), the pt + pin has a standard pwm signal and may be directly connected to the gate of a primary-side mosfet, while a reference clock is generated on the pt C pin. pgnd (pin 27/pin 24): gate driver ground pin. connect to power ground at the source of the synchronous mosfet. v cc (pin 28/pin 25): main v cc input for all driver and control circuitry. ltc3766 3766fa
10 for more information www.linear.com/ltc3766 b lock diagra m + ? + ? + ? + ? swhi pgnd wait ovp 1.4v sw v cc fg pgnd v cc sg v cc v cc pt + pt ? v sec swhi c v sec(th) v sw 50v 30v 5.5ma limit 4vsb 1.22v v in(uv) v cc(uv) v cc sd pgnd pulse xfmr adaptive blanking and delay driver encoding and logic ? ? main xfmr ? ? fgd sgd a en 275k en 12a 1.21v sw 3766 bd v in sense v out sense i peak adjust hv linreg disable 1.22v 4vsb lv: 4.7v/4.5v hv: 8v/7.7v lv: 4.7v/3.9v hv: 7.9v/6.9v a lv: 58k hv: 46k 5v to 32v dc 5v to 15v dc v in v cc v aux regsd i pk ndrv gnd v ref reg uvlo sd 4vsb wait sslo overcurrent uvlo v in 80k + ? amp differential amplifier + ? 29.3x 2.2x 0.305v ? + + + + i s + 2v 0.60v g m = 2.7ms error amplifier ss + ? c + ? c oc 2.93v itrp pwm reset dominant peak current comparator dmax overcurrent wait ovp skip + ? c + ? r s q r s q + ? c ripple cancellation + i s ? fb ith 0.2v 1.9v blank blank dmax swhi + ? ea fs/sync phase pt + /pt ? drive type (pulse encoded/standard) + ? c slope comp osc and pll soft- start blanking drive/v cc control mode hv/lv mode ss fb v sout v s + run 80k 80k 80k v s ? ltc3766 3766fa
11 for more information www.linear.com/ltc3766 ti m ing diagra m v pt + ? v pt ? v in v in ? 0v ltc3765 ag ltc3765 pg swp node pulse encoded pwm v in 1 ? duty cycle ~ 0v set by ltc3766 fgd pin set by ltc3765 delay pin pwm on time set by ltc3766 sgd pin fixed 180ns delay 0v ltc3766 sg ltc3766 fg sw node swb node n s n p v out 1 ? duty cycle ~ 3766 td01 ag ag pg pg swp in + in ? ltc3765 ? ? ? ? 3766 f01 sg v out + v out ? v in + v in ? sw swb sw fg pt + fg pt ? sg ltc3766 figure 1. reference schematic for timing diagram ltc3766 3766fa
12 for more information www.linear.com/ltc3766 o pera t ion the ltc3766 is a secondary-side pwm controller designed for use in a forward converter with active clamp reset and synchronous rectification. when used in conjunction with the ltc3765 active-clamp forward controller and gate driver, it forms a highly efficient and robust isolated power supply with a minimum number of external components. by making use of a secondary-side control architecture, the ltc3766 is able to provide exceptional transient response while directly monitoring the load to ensure that both output voltage and output current are precisely controlled. this architecture provides superior performance and greater simplicity, and is particularly well suited to high power battery charger applications. self-starting start-up in most applications, the ltc3766 will be used with the ltc3765 to create a self-starting forward converter with secondary-side control. since there is initially no bias voltage available on the secondary side, the ltc3765 must manage the start-up in an open-loop fashion on the primary side. when power is first applied on the primary side, the ltc3765 begins an open-loop soft-start using its own internal oscillator. power is supplied to the secondary by switching the main primary-side mosfet with a gradu - ally increasing duty cycle from 0% to 70%, as controlled by the rate of rise of the voltage on the ssfl t pin. on the s econdary side, bias voltage can be generated directly from the main transformer using a peak charge circuit, or other technique as appropriate. when the ltc3766 has adequate voltage to satisfy its start-up requirements, it provides duty cycle information through the pulse transformer as shown in figure 2. the ltc3765 detects this signal and transfers control of the gate drivers to the ltc3766, which continues the soft-start of the output voltage. typically, this hand-off from primary to secondary occurs when the output voltage is less than one half of its final level. the ltc3765 then turns off the linear regulator and, through an on-chip rectifier, extracts bias power for the primary- side mosfets from this signal. linear regulators in general, the bias voltage generated on the secondary side is higher than the level desired for operation of the forward and synchronous mosfets. consequently, the ltc3766 contains a high voltage linear regulator controller as well as a 15v v aux bypass regulator with an internal pmos, either of which can be used to regulate the volt- age on the v cc pin. the linear regulator controller is used by tying the ndrv pin to the base or gate of an external n - type pass device. the l tc3766 v in pin provides bias to the linear regulator controller as well as to internal standby and monitoring circuitry. if adequate voltage is detected on the v aux pin, then the v aux bypass regulator will be activated and the high voltage linear regulator controller will be shut down to reduce power loss. alternatively, if only the v aux regulator is needed, then the ndrv pin can be tied off to v cc , while v in is tied to v aux . this flexible arrangement of two linear regulators allows for the con- venient and efficient generation of v cc bias voltage for a wide array of applications. using the mode pin, the output voltage of both linear regulators can be set to either 7v or 8.5v, depending on the level needed to drive the gates of the forward and synchronous mosfets. note that the undervoltage lock - out (uvlo) set points as well as v aux switchover levels are adjusted along with the v cc regulation levels. this ensures that the mosfets are only switched when there is adequate gate drive voltage. run control and soft-start the main on/off control for the ltc3766 is the run pin. this pin features precision thresholds with both internal and externally adjustable hysteresis. this pin can be used to monitor the secondary-side bias voltage or main output voltage, thereby controlling the point at which hand-off from primary to secondary side occurs. alternatively, it can be driven directly with a control signal. in nonisolated applications when the ltc3766 is used standalone, this pin can be used as an undervoltage lockout by monitoring the main power supply input voltage. see nonisolated applica - tions in the applications information section for details. the l tc3766 will begin a soft-start sequence when the run pin is high, adequate voltage is present on both the v in and v cc pins, and switching is detected on the sw pin. note that the ltc3766 must see switching on the sw pin prior to initiating a soft-start sequence to ensure that the ltc3765 is ready for control hand-off. the soft-start sequence begins by first measuring the voltage on the fb ltc3766 3766fa
13 for more information www.linear.com/ltc3766 o pera t ion pin and then rapidly pre-setting the soft-start capacitor voltage to a level that corresponds to the output voltage, v out . this is done to provide a smooth ramp on the output voltage as control is transferred from primary to secondary, as well as to avoid any unnecessary start-up delay. once the soft-start capacitor has been pre-set to the appropriate level, the ltc3766 then sends a brief sequence of pulses through the pulse transformer to establish a communica - tion lock between the ltc3766 and the ltc3765. at this point, the ltc3766 assumes control of the primar y-side mosfets, and the soft-start capacitor begins charging with a constant current of 5a, continuing the soft-start of the main output voltage. note that the soft-start volt - age is used to limit the effective level of the reference into the error amplifier . this technique maintains closed-loop control of the output voltage during the secondar y-side soft-start interval. gate drive encoding since the ltc3766 controller normally resides on the secondary side of an isolation barrier, communication to the primary-side gate driver must be done through a small pulse transformer. a common scheme for communicating gate drive (pwm) information makes use of short pulses and relies on receiver latches to remember whether power mosfets should be either on or off. however, this system is prone to get into the wrong state, and has difficulty distinguishing a loss of signal from a legitimate zero duty cycle signal. to alleviate these concerns, the ltc3766 uses a proprietary gate drive encoding scheme that reliably maintains constant contact across the isola - tion barrier without introducing any delay. the ltc3766 encodes pwm information onto the pt + and pt C outputs, which are in turn connected to a small pulse transformer through a dc-blocking capacitor. these outputs are driven in a complementary fashion, with a constant 79% duty cycle. this results in a stable volt- second balance, so that the signal amplitude transferred across the pulse transformer is constant. as shown in figure 2, the beginning of the interval when (v pt + -v pt C ) is positive approximately coincides with the turn-on of the main primary-side mosfet. likewise, the beginning of the interval when (v pt + -v pt C ) is negative coincides with the maximum duty cycle (forced turn-off of main primary- side mosfet). at the appropriate time during the positive interval, the end of the on time (pwm going low) is signaled by briefly applying a zero-volt differential across the pulse transformer. in the event that a zero duty-cycle signal needs to be sent, this is accomplished naturally by placing the zero-voltage differential at the beginning of the positive interval. in this manner, any duty cycle from 0% to the maximum of 79% can be sent across the pulse transformer without delay. figure?2 illustrates the operation of this encoding scheme. figure 2: gate drive encoding scheme (mode = gnd or mode = v cc ) 150ns +v cc ?v cc 1 clk per v pt + ? v pt ? 150ns 3766 f02 1 clk per on the primary side, the ltc3765 receives the signal from the pulse transformer through a dc restoring capacitor. after communication lock has been established between the two parts, the ltc3765 extracts clock and duty cycle information from the signal and uses it to control its gate driver outputs. note that, except for a tiny pulse, this scheme is constantly applying a differential voltage across the pulse transformer. therefore, the ltc3765 can almost instantly detect a loss of signal and shut off the power mosfets. forward converter and main loop operation once communication lock has been established between the ltc3766 and the ltc3765, the ltc3766 will have control over the switching of the primary-side mosfets. during normal operation, the main primary-side mosfet (connected to pg on the ltc3765) is turned on somewhat after the forward mosfet on the secondary side. this applies the input voltage across the transformer, causing the sw node on the secondary side to rise. since the sw node voltage is greater than the output voltage, the inductor current ramps upward. when the current in the inductor ltc3766 3766fa
14 for more information www.linear.com/ltc3766 o pera t ion has ramped up to the peak value as commanded by the voltage on the ith pin, the current sense comparator trips, turning off the primary-side mosfet. after a short delay, the forward mosfet is turned off and the synchronous mosfet is turned back on, causing the inductor current to ramp back downwards. at the next rising edge of the ltc3766 internal clock, the cycle repeats as the synchro - nous mosfet is turned off and the forward and main primar y-side mosfet s are again turned on. the ltc3766 error amplifier senses the main output voltage, and adjusts the ith voltage to obtain the peak inductor current needed to keep the output voltage at the desired regulation level. in some applications, there can be considerable resistive voltage drops between the main output voltage and the load. to address this, the ltc3766 contains a precision differential amplifier, which can be used to remotely sense a load voltage as high as 15v. current sensing, slope compensation and blanking the ltc3766 supports current sensing either with a current sense resistor or with an isolated current transformer. when using a current sense resistor, the i s + and i s C pins operate differentially, and the maximum peak current threshold is approximately 75mv. normally, the current sense resistor is placed in the source of the forward mosfet to minimize power loss. if a current transformer is used to sense the primary-side switch current, then the i s C input should be tied to v cc and the i s + pin to the output of the current transformer. this causes the gain of the internal current sense amplifier to be reduced, so that the maximum peak current threshold is increased to approximately 1v. as with any pwm controller that uses constant-frequency peak current control, slope compensation is needed to provide current-loop stability and improve noise margin. the ltc3766 has fixed internal slope compensation. the amount of slope has been chosen to be adequate for a wide range of applications. normally, the use of slope com - pensation would have a negative impact on the accuracy of the current limit, but the ltc3766 uses a proprietary circuit to nullify the effect of slope compensation on the current limit performance. since the ltc3766 current loop is sensing switch cur - rent, leading edge blanking is needed to avoid a current comparator false trip due to the mosfet turn-on current spike. the ltc3766 uses the voltage on the sw pin (tied to the drain of the synchronous mosfet) to implement an adaptive leading-edge blanking of approximately 180ns. the blanking of the current comparator begins only after the voltage on sw has risen above 1.4v. this adaptive blanking is essential because of the potentially long delay from the time that pt + rises to the time that the sw node rises, and current begins ramping up in the output inductor. this blanking also minimizes the need for external filtering. gate driver delay adjustment as in all forward converters, the main transformer core must be properly reset so as to maintain a balanced volt- second product and prevent saturation. this job is handled on the primary side by the ltc3765, which features an active clamp gate driver. the active clamp mosfet works together with a capacitor to generate an optimal reset volt - age for the main transformer. this optimal reset voltage minimizes voltage stress on the main primar y-side mosfet and maximizes the utilization of the power transformer core by reducing the magnetic flux density excursion. in general, the active clamp mosfet is switched in a complimentary fashion to the main primary-side mosfet. since the active clamp mosfet is a pmos, the active clamp gate driver (ag) and the main primary-side gate driver (pg) voltages are therefore in-phase, with a programmable overlap time set by the ltc3765 delay pin. the delay time between the active clamp pmos turn-off and the primary switch nmos turn-on is critical for opti - mizing efficiency. when the active clamp is on, the drain of the primary nmos, or primar y switch node (swp), is driven to a voltage of approximately v in /(1Cd) by the main transformer. when the active clamp turns off, the current in the magnetizing inductance of the transformer ramps this voltage linearly down to v in . power loss is minimized by turning on the primary switch when the swp voltage is at a minimum. a resistor from the ltc3765 delay pin to ground sets a fixed time for the pg turn-on delay. the delay time between the primary switch turn-off and the active clamp turn-on is substantially less critical. when the primary switch turns off, the main transformer leakage inductance is biased with the peak current of the ltc3766 3766fa
15 for more information www.linear.com/ltc3766 o pera t ion inductor reflected through the transformer. this current drives the voltage across the active clamp pmos quickly to 0v. turning on the pmos after this transition results in minimal switching power loss. the ltc3765 active clamp turn on delay is internally fixed to 180ns, which normally achieves zero voltage switching on the active clamp pmos. on the secondary side, the turn-on delay of the forward gate (fg) and synchronous gate (sg) mosfets are adjusted by the fgd and sgd pins respectively. these delays are set using resistors to gnd so as to minimize the dead time (when the load current is being carried by mosfet body diodes) while avoiding shoot-through with the primary-side mosfets. a shoot-through condition exists if either the pg and sg gates, or the ag and fg gates are high at the same time. note that the sg mosfet turn-on delay has a minimum limit that is established by the falling edge of the sw node. the sg pin will not go high until sw has falling below 0.5v. refer to delay resistor selection in the applications information section for more detailed information. in standalone mode (100k or 50k resistor on mode) the dead time between pg and sg is set adaptively to prevent shoot-through. frequency setting and synchronization the ltc3766 uses a single pin to set the operating frequency or to synchronize the internal oscillator to a reference clock using and on-chip phase-locked loop (pll). the fs/sync pin sources a 20a current, and it may be tied to v cc for fixed 275khz operation or have a single resistor to gnd to set the switching frequency to f sw = 4r fs . if a clock signal (>2v) is detected at the fs pin, the ltc3766 will automatically synchronize to the falling edge of this signal using an internal pll. current limit and inductor ripple cancellation since the ltc3766 utilizes peak current control, the peak inductor current is limited when the load current demand increases above the current limit set point. the peak current limit is established by an internal clamp on the maximum level of the ith voltage. the average current, however, will be less than the peak current by an amount equal to one-half of the inductor ripple current. during current limit, this ripple current will change significantly with variations in v in , v out and switching frequency. without inductor ripple cancellation, this variation in ripple current would also result in an average output current that changes significantly, even though the peak current is held at a constant value. in order to keep the average current approximately constant during current limit, the ltc3766 cancels the effect of the ripple current by adjusting the value of the peak current limit (or ith clamp level) in proportion to the amount of inductor ripple current. this is achieved by generating an internal ramp that mimics the inductor current ramp, and then adding the amplitude of this internal ramp to the ith clamp voltage on a cycle-by cycle basis. during the on time, the slope of the inductor current is given by: di l dt = v sw ? v s + l the ltc3766 establishes a voltage on the i pk pin of (v sw C v s + )/15, which is one-fifteenth of the voltage across the output inductor during the on-time when sw is high. by choosing a resistor r ipk that is proportional to the value of the output inductor (r ipk = kl), the current flowing in r ipk becomes proportional to the slope of the inductor current: i ripk = v sw ? v s + 15r ipk = v sw ? v s + 15kl during the time when sw is high, the ltc3766 uses the r ipk current to create an internal ramp by charging an on-chip capacitor c rip . the slope of this internal ramp voltage is given by: dv ramp dt = i ripk c rip = v sw ? v s + 15klc rip the amplitude of this internal ramp is then added to the ith clamp level dynamically. by choosing the appropri - ate value of r ipk , therefore, the average current during current limit will be essentially independent of changes in ripple current. as is the case with all dc/dc converters that maintain constant frequency operation, a cycle by cycle current limit is only effective at duty cycles where the on time is ltc3766 3766fa
16 for more information www.linear.com/ltc3766 o pera t ion greater than the minimum controllable on-time. under short-circuit conditions, for example, the ltc3766 limits the current using a separate overcurrent comparator. when this overcurrent comparator is tripped, the ltc3766 gener - ates a fault followed by a soft-start retry. this hiccup mode over current protection is highly effective at minimizing power losses under short-cir cuit conditions. direct flux limit in active clamp forward converters, it is essential to es - tablish an accurate limit to the transformer flux density in order to avoid core saturation during load transients or when starting up into a pre-biased output. although the active clamp technique provides a suitable reset voltage during steady-state operation, the sudden increase in duty cycle caused in response to a load step can cause the transformer flux to accumulate or walk, potentially lead - ing to saturation. this occurs because the reset voltage on the active clamp capacitor cannot keep up with the rapidly changing duty cycle. this effect is most pronounced at low input voltage, where the voltage loop demands a greater increase in duty cycle due to the lower voltage available to ramp up the current in the output inductor. traditionally, transformer core saturation has been avoided either by limiting the maximum duty cycle of the converter or by slowing down the loop to limit the rate at which the duty cycle changes. limiting the maximum duty cycle does help the converter avoid saturation for a load step at low input voltage, since the duty cycle maximum is clamped; however, transformer saturation can also easily occur at higher input voltage where the maximum duty cycle clamp is ineffective. limiting the rate of duty cycle change such that the active clamp capacitor can sufficiently track the duty cycle change also helps to prevent saturation in many situations, but results in a very poor transient response. neither of these traditional techniques is guaranteed to prevent the transformer from saturating in all situations. for example, saturation can easily occur using these traditional techniques when starting up into a pre-biased output, where the duty cycle can quickly change from 0% to 75%. moreover, neither of these traditional techniques is able to prevent saturation in the negative direction, which can result from sudden decreases in duty cycle. the ltc3765 and ltc3766 implement a new unique system for monitoring and directly limiting the flux accumula - tion in the transformer core. during a reset cycle, when the active clamp pmos is on, the magnetizing current is directly measured and limited through a sense resistor in series with the pmos source. this prevents saturation in the negative direction. when the pmos turns off and the main nmos switch turns on, the ltc3765 generates an accurate internal estimate of the magnetizing current based on the sensed input voltage on the ltc3765 run pin and transformer core parameters customized to the particular core by a resistor from the ltc3765 r core pin to ground. the magnetizing current is then limited during the on-time by this accurate internal approximation. unlike previous methods, the direct flux limit directly measures and monitors flux accumulation and guarantees that the transformer will not saturate in either direction, even when starting into a pre-biased output. this technique also provides the best possible transient response, as it will temporarily allow very high duty cycles, only limiting the duty cycle when absolutely necessary. moreover, this technique prevents overcurrent damage to the active clamp pmos, which is a potentially significant weakness in many active clamp forward converter designs. additional protection features the ltc3766 contains a wide array of protection features, which protect the dc/dc converter in the event that ab - normal conditions persist. in general, protections features are either classified as a fault or a limit. when a fault is detected, all switching stops and the l tc3766 initiates a soft-start retr y. faults of this nature include overcurrent, overtemperature, differential amplifier miswire and communication-lock fault. an overcurrent fault occurs if the peak current exceeds approximately 133% of its normal value during current limit. note that when inductor ripple cancellation is used, the value of the peak current during current limit will vary with inductor current ripple. the overtemperature fault is set at 165c, with 20c of hysteresis. this is helpful for limiting the temperature of the dc/dc converter in the event of some external device failure or other abnormal condition. the differential amplifier wiring fault is gener - ltc3766 3766fa
17 for more information www.linear.com/ltc3766 o pera t ion ated if the inputs on the differential amplifier are reversed, or if there is not enough voltage on the v in pin to support the voltage needed on v sout . this is important to avoid an overvoltage condition on the output. finally, since it is essential that the ltc3766 be in constant communication with the ltc3765, a loss of communication lock will also generate a fault. a lock condition is detected by monitoring the sw node voltage, and ensuring that it is both rising and falling as it should in response to the pwm signal being sent to the primary side. if the sw node voltage is not rising and falling in an appropriate manner, than a lock fault is generated. in addition to the four protection features that generate faults, there are also four protection features that establish a clamp or limit, without generating a fault. first, the ltc3766 contains a precision volt-second clamp. this feature is not needed when the ltc3766 is used in conjunction with the ltc3765, which incorporates the direct flux limit feature. if the ltc3766 is used standalone, however, the volt-second limit can be used by placing a resistor from the sw node to the v sec pin and a capacitor from v sec to gnd. when the sw node is low, the capacitor is discharged by an on-chip nmos. when the sw node is high, the capacitor on v sec is charged. if the capacitor voltage exceeds an internally generated threshold, then the main primary switch will be turned off, thereby limiting the volt-second product applied to the main transformer. to compensate for the exponential nature of the rc charging circuit, the ltc3766 adjusts the threshold of the volt-second comparator according to: v sec(th) = 0.6 ? 0.16 v sw(hi) where v sw(hi) is the voltage on the sw pin during the on-time of the primary switch. this keeps the volt-second limit essentially constant for sw node voltages in the range of 2v to 40v. second, in the event that the main output voltage exceeds its regulation target by more than 17%, the ltc3766 will detect an overvoltage condition. if this happens, the ltc3766 will immediately turn off the main primary mosfet and turn on the synchronous mosfet. this has the effect of pulling down the output voltage to protect the load from potential damage. overvoltage protection is not latched, and normal operation is restored when the output voltage has been reduced to within 15% of its regulation level. third, the ltc3766 contains an adjustable synchronous mosfet reverse overcurrent. this is accomplished by monitoring the sw voltage when the synchronous mosfet is on (sg pin is high). if the voltage on sw exceeds a pre-determined threshold, then the synchronous mosfet will be turned off, protecting it from potentially damaging current levels. this sw threshold for reverse overcurrent detection can be reduced by placing a resistor in series with the sw pin, which sources a current when the sg pin is high. note that the sg reverse overcurrent thresh - old and the sw pin source current are adjusted based on the state of the mode pin. this is done to accommodate the use of either high voltage or low voltage mosfets, which normally have significantly different on resistances. in an overvoltage condition, the sg reverse overcurrent will override the overvoltage protection and force sg low, essentially regulating the reverse sg mosfet current at a high level while the overvoltage condition persists. however, the sg reverse overcurrent is only active after the ltc3766 has achieved communication lock. finally, the regsd pin can be used to limit the amount of time that the high voltage linear regulator controller is active. this is particularly useful when the ltc3766 is used standalone in a nonisolated forward converter. in this application, the pass device of the linear regulator controller may be dissipating considerable power. when the linear regulator controller is active, the regsd pin sources a 13a current. if a capacitor from regsd to gnd charges to a voltage greater than 1.21v, then linear regulator controller is disabled. gate driver mode control in addition to being used in conjunction with the ltc3765, the ltc3766 can also be used standalone in a nonisolated forward converter application. in this case, the mode pin can be used to disable gate drive encoding by tying mode to gnd through either a 100k (for v cc = 7v operation) or 50k (for v cc = 8.5v operation) resistor. this causes a normal pwm signal to appear on pt + and a reference clock to appear on pt C . ltc3766 3766fa
18 for more information www.linear.com/ltc3766 a pplica t ions i n f or m a t ion secondary-side bias and start-up in most applications, the ltc3766 will receive its bias voltage from a supply that is generated on the secondary side. the manner in which the secondary bias is generated depends upon the output voltage as well as the variation in the input voltage of the dc/dc converter. in all applications, however, the secondary bias must always come up before the output reaches the regulation level. this is essential to avoid an overvoltage condition on the output, since the initial start-up is performed from the primary side in an open-loop fashion. see generating the secondary-side bias for more information. note that the ltc3766 will not begin a soft-start sequence and initiate switching until the run pin is high, adequate voltage is present on both the v in and v cc pins, and switching is detected on the sw pin. the ltc3766 looks for switching on the sw pin to ensure that the ltc3765 is active and ready for control hand-off. for switching to be detected, the sw node waveform must have at least eight consecutive pulses in the range of 50khz to 700khz. the sw node waveform must also have a peak that is greater than 1.4v and a valley that is less than 0.5v. in standalone mode, the ltc3766 begins the soft-start sequence without waiting for a switching waveform to be detected on the sw pin. linear regulator operation the ltc3766 contains two linear regulators that are used to regulate the available bias voltage down to a level suitable for driving mosfets. if the bias supply voltage is greater than 15v, then the high voltage linear regulator controller may be used. this makes use of an external n-type pass device. place a capacitor of 0.22f or greater on v in and 1f or greater on v cc . if the bias supply connected to the v in pin has a relatively high output impedance, it may be necessary to use a larger capacitor on v in to prevent the v in pin voltage from dropping when the v cc capacitor is being charged. the v cc charge rate during linear regulator start-up is set by the ltc3766 to approximately 0.5v/s, which will create at charging current of (0.5 ? 10 6 ) c vcc . care should be taken to ensure that this charging current does not exceed the soa of the n-type pass device, par - ticularly when operating at higher v in voltages. the v cc regulation level can be set to either 7v or 8.5v as desired using the mode pin. see the section on v cc and drive mode selection for details. the ltc3766 also contains a 15v internal bypass ldo. if the voltage on the v aux pin exceeds the v aux switchover threshold, then the high voltage linear regulator is disabled, and an internal pmos-pass ldo uses the v aux voltage to supply power to v cc . this allows the high voltage linear regulator to be used for initial start-up and the higher ef - ficiency bypass ldo to be used during normal operation. figure 3 illustrates such a configuration that uses both linear regulators. if the voltage on the v aux pin is below the switchover threshold, then the v aux pin is internally loaded with a resistance of approximately 920. this internal load is removed after the v aux regulator is enabled, and is used to ensure that the v aux supply is reasonably stiff before the bypass regulator is activated. in some cases, it is desirable to use the high voltage linear regulator only briefly during start-up, so as to limit the temperature rise in the external pass device. to accomplish this, place a capacitor on the regsd pin to ground (see figure 3) such that: c rsd = t hvreg 13a ( ) 1.21v where t hvreg is the time that the high voltage regulator will operate. when the high voltage regulator is operat - ing, a 13a current is sourced from the regsd pin, and when it is shut down (e.g., the bypass regulator is ac - tive), a 3a current is sinked into the regsd pin. if the regsd voltage exceeds 1.21v , the high voltage regulator is disabled. choose a time t hvreg that is greater than the normal start-up time. after start-up, if the voltage on the v aux pin drops, the high-voltage linear regulator will be re-energized, but only for a limited time. v in ndrv ltc3766 optional v cc c vaux c vcc 3766 f03 c vin c rsd v aux regsd lv bias supply 5v to 15v hv bias supply 6v to 32v figure 3. typical linear regulator connections ltc3766 3766fa
19 for more information www.linear.com/ltc3766 a pplica t ions i n f or m a t ion when used with a bias supply that is between 5v and 10v, the v cc pin can be directly connected to the bias supply as shown in figure 4a. note that the v in and ndrv pins must also be connected to the bias supply for proper operation of internal circuitry. when a bias supply between 6v and 15v is available, the v aux bypass linear regulator can be used standalone as shown in figure 4b. in this case, proper start-up is assured by connecting the ndrv pin to v cc . since there is no external pass device on ndrv, however, the effective uvlo levels will be dictated by the v aux switchover thresholds instead of the v cc uvlo thresholds. rather than relying on the v aux thresholds, the start-up and shutdown levels are normally set by using the run pin to monitor the bias supply voltage as shown in figure?4b. see the run pin operation section for details. for applications where the available bias supply is greater than 30v, the ltc3766 also contains a current-limited 30v clamp on the v in pin. this clamp can sink up to 3.5ma to allow the v in pin to be used as a shunt regulator. this is especially useful in nonisolated applications where the ltc3766 is used standalone. see the nonisolated applica - tions section for more information. run pin operation normal operation is enabled when the voltage on run rises above its 1.22v threshold. as shown in figure 5, the run pin can be used with an external resistor divider to enable the ltc3766 operation based on a sensed volt - age v x . in self-starting applications, v x is normally either the converter output voltage (v out ) or a bias voltage. in nonisolated applications, v x is normally the converter input voltage (v in ). see nonisolated applications for more information on the use of the run pin in nonisolated applications. run r1 r2 ltc3766 v x gnd 3766 f05 figure 5. using the run pin to determine start-up v in ltc3766 v cc 3766 f04a c vcc ndrv lv bias supply 5v to 10v v in v aux ltc3766 v cc c vcc 3766 f04b c vaux r1 ndrv run lv bias supply 6v to 15v r2 figure 4a. no linear regulator used figure 4b. v aux regulator used standalone a 3a current is pulled into the run pin when it is below its threshold that, when combined with the value chosen for r1, increases the hysteresis beyond the internal amount of 4%. when used in this manner, the values for r1 and r2 can be calculated from the desired rising and falling v x thresholds by the following equations: r1 = v x(rising) ? 1.043 ? v x(falling) 3a r2 = 1.17 ? r1 v x(falling) ? 1.17 in self-starting applications where the ltc3765 performs an open-loop soft-start, the voltage v x can be tied to v out of the converter (v x = v out ) to inhibit the ltc3766 start- up until the output voltage is above a given level. this sets the exact output voltage at which soft-start control is handed off from primary to secondary. this hand-off output voltage should be set high enough so as to avoid pulse-skipping operation when the ltc3766 initially takes ltc3766 3766fa
20 for more information www.linear.com/ltc3766 a pplica t ions i n f or m a t ion control. if excessive pulse skipping occurs in applications that use a peak charge circuit to generate bias voltage, this can cause the bias supply to fall, preventing proper start- up. to preclude this possibility, use the run pin to inhibit the ltc3766 start-up until the output voltage is at least: v out(on) > 300ns n s f sw v in(max) n p note that in self-starting applications, direct run/stop control should be handled only on the primary side using the ltc3765. if the ltc3765 gets disabled, the ltc3766 will sense that the primary side is no longer switching and automatically shut down. to avoid a possible output overvoltage, do not manually disable the ltc3766 unless the ltc3765 is also manually disabled. if the run pin function is not needed, it can be tied directly to the v in pin. setting the switching frequency and synchronization the switching frequency of the ltc3766 is set using the fs/sync pin. this pin sources a 20a current, and a re - sistor to ground on this pin sets the switching frequency to a value equal to: f sw = 4r fs alternatively, the fs/sync pin can be tied to v cc , which sets the switching frequency to a fixed value of 275khz. in general, a higher switching frequency will result in a smaller size for inductors and transformers, but at the cost of reduced efficiency. although the ltc3766 can operate from 75khz to 500khz, the best balance between efficiency and size for a forward converter is found when operating between 150khz and 350khz. if a clock signal (>2v) is detected at the fs pin, the ltc3766 will automatically synchronize to the falling edge of this sig - nal. table 1 summarizes the operation of the fs/sync pin. table 1 fs/sync pin switching frequency v cc 275khz r fs to gnd f sw = 4r fs reference clock f sw = f ref (100khz to 500khz) in polyphase applications, synchronization can be achieved by tying the pt C pin of the master to the fs/sync pin of each slave. the relative phase delay of each slave is set using the phase pin. any one of five preset values can be selected as shown in table 2. note that the phase delay is relative to the falling edge of the incoming reference clock on the fs/sync pin, since the falling edge of pt C corresponds to the beginning of the pwm cycle. table 2 phase pin phase delay application gnd 180 2-phase and 4-phase 25k to gnd 240 3-phase 50k to gnd 120 3-phase 100k to gnd 90 4-phase 100k to v cc 270 4-phase in some applications, it is desirable to start switching at a given frequency, and then synchronize to a clock reference signal at a later time. this can be accomplished by using the circuit shown in figure 6. fs/sync ltc3766 gnd r fs bat54 50k clk 2n2222a 10nf 10k 3766 f06 figure 6. synchronization after free running once the ltc3766 has been synchronized, do not remove the external synchronizing clock unless the ltc3766 is also shut down. removal of the external clock after synchronization will result in operation at low frequencies for a period of time, which can lead to very high currents in external power components. setting the output voltage the ltc3766 output voltage is set by an external feedback resistor divider placed across the output as shown in figure 7. the regulated output voltage is determined by: v out = 0.6v ? 1 + r b r a ? ? ? ? ? ? ltc3766 3766fa
21 for more information www.linear.com/ltc3766 a pplica t ions i n f or m a t ion be careful to keep these divider resistors very close to the fb pin to minimize the trace length and noise pick-up on the sensitive fb signal. using a low resistance (<2k) for the output voltage divider also minimizes noise on the fb pin. if the remote sense amplifier is used, then the divider should be placed between the v sout pin and gnd. see the remote sensing section for details. of power level, choose a family of transformers whose rated power level exceeds that of the required amount of output power. be careful to allow for room to grow, as the power requirements of many electronic systems tend to increase throughout development. once a family of transformers has been selected, the next step is to choose a suitable transformer from within that family. this mainly consists of choosing the correct number of primary and secondary turns (n p and n s ). the value of n s can be calculated from: n s = 10 8 v out f sw a c b m where a c is the cross-sectional area of the core in cm 2 (as normally given in the transformer data sheet) and b m is the maximum ac flux density desired. for the pulse pa08xx series power transformers used in the typical applications section, a c = 0.59cm 2 . for the pulse pa09xx series power transformers, ac = 0.81cm 2 . most high frequency trans - formers use a ferrite core material. consequently, selecting a maximum ac flux density of 2000 gauss is normally a good starting point, provided that the switching frequency is between 150khz and 350khz. this value of b m leaves headroom during transients and avoids excessive core losses. note that the choice of b m together with switch - ing frequency will determine the amount of core loss for a given transformer . consult the transformer data sheet to evaluate the resulting core loss and temperature rise. in some cases, it may be necessar y to increase n s somewhat in order to reduce b m and the associated temperature rise. in all cases, be sure to stay well below the saturation flux density of the transformer core. once the value of has n s been selected, the required transformer turns ratio can be calculated from n p n s = d max v in(min) v out where v in(min) is the minimum input voltage and d max is the maximum duty cycle. although the ltc3766 has a maximum duty cycle of 79% (d max = 0.79), normally a lower value of d max is chosen in the above equation so that there is duty cycle headroom to accommodate load figure 7. setting the output voltage v fb r b r a ltc3766 v out 3766 f07 selecting the main transformer the job of the transformer in a forward converter is to step the voltage either up or down while providing isola - tion between the primary and secondary grounds. ideally, this transformer would not store any energy (it would have infinite magnetizing inductance). note that this objective is very different from that of the transformer used in a flyback converter . the transformer used in a flyback con - verter is really a coupled inductor, the purpose of which is to store energy during the primar y-side on time and then deliver it to the secondary during the off-time. in a forward converter, by contrast, the power is transferred during the primary-side on-time, and the off-time is used to recover the small amount of energy that was inadvertently stored in the core of the transformer. for nearly all applications, an off-the-shelf transformer can be selected. transformers using planar winding technology are widely available and are a good choice for minimizing leakage inductance as well as component height. there are two basic items to consider in selecting an appropri - ate family of off-the-shelf transformers: 1) the isolation requirements and 2) the power level requirements. if the application circuit has specific isolation requirements, choose a family of transformers whose isolation level satisfies that requirement. in addition to an isolation volt - age rating, the application may require a transformer with certification from a particular agency , or it may require a specific type of isolation (e.g., basic or functional). in terms ltc3766 3766fa
22 for more information www.linear.com/ltc3766 a pplica t ions i n f or m a t ion transients when operating at minimum input voltage. a value for d max of 0.65 to 0.70 is appropriate for most applications. having selected a particular transformer, calculate the copper losses associated with the transformer winding. these losses are highest when operating at maximum duty cycle and full load. however, it is better to evaluate copper losses at the nominal operating point of 50% duty cycle, where the losses are approximately: p cu = i max ( ) 2 2 r sec + n s n p ? ? ? ? ? ? 2 r pri ? ? ? ? ? ? ? ? where r pri and r sec are the primary and secondary winding resistances respectively, and i max is the maxi- mum output current. an optimal transformer design has a reasonable balance between copper and core losses. if they are significantly different, then adjust the number of secondar y turns (and recalculate the needed turns ratio) to achieve such a balance. inductor v alue calculation the selection of an output inductor is essentially the same as for a buck converter. for a given input and output volt - age, the inductor value and operating frequency determine the ripple current. the ripple current ? i l increases with higher v in and decreases with higher inductance: i l = v out f sw l 1? v out v in ? n p n s ? ? ? ? ? ? accepting larger values of ?i l allows the use of low in - ductances, but results in higher output voltage ripple and greater core losses. a reasonable starting point for setting the ripple current is ? i l = 0.3(i out(max) ) for nominal v in . the maximum ?i l occurs at the maximum input voltage. inductor core selection once the value for l is known, the type of inductor must be selected. high efficiency converters generally cannot afford the core loss found in low cost powdered iron cores, forcing the use of the more expensive ferrite cores. actual core loss is essentially independent of core size for a fixed inductor value but it is very dependent on the inductance selected. as the inductance increases, core losses decrease. unfortunately, increased inductance requires more turns of wire and therefore copper losses will increase. ferrite designs have very low core losses and are pre - ferred at high switching frequencies, so design goals can concentrate on copper loss and preventing saturation. ferrite core material saturates hard, which means that in duct ance collapses abruptly when the peak design current is exceeded. this results in an abrupt increase in inductor ripple current and consequent output voltage ripple. do not allow the core to saturate! active clamp capacitor the active clamp capacitor, c cl , stores the average reset voltage of the transformer over many cycles. the voltage on the clamp capacitor is generated by the transformer core reset current, and will intrinsically adjust to the optimal reset voltage regardless of other parameters. the voltage across the capacitor at full load is approximately given by: v cl = v in 2 v in ? 1.15 v out ? n p n s ? ? ? ? ? ? n p /n s is the main transformer turns ratio. the factor of 1.15 accounts for typical losses and delays. when pg and ag on the ltc3765 are low, the bottom side of the clamp capacitor is grounded, placing the reset voltage, v cl , on the swp node. when pg and ag are high, the top side of the capacitor is grounded, and the voltage on the bottom side of the capacitor is Cv cl . therefore the voltage seen on the capacitor is also the voltage seen at the drains of the pg and ag mosfets. as shown in figure 8, the v cl voltage has a minimum when the converter is operating at 50%. for a given range on v in , therefore, the maximum clamp voltage (v cl(max) ) will occur either at the minimum or maximum v in , depending on which input voltage causes the converter to operate furthest from 50% duty cycle. the maximum v cl voltage can be determined by substituting the maximum and minimum values of v in into this equation and selecting the larger of the two. in order to leave room for overshoot, ltc3766 3766fa
23 for more information www.linear.com/ltc3766 a pplica t ions i n f or m a t ion choose a capacitor whose voltage rating is greater than this maximum v cl voltage by 50% or more. typically, a good quality (x7r) ceramic capacitor is a good choice for c cl . also, be sure to account for the voltage coefficient of the capacitor. many ceramic capacitors will lose as much as 50% of their value at their rated voltage. the value of the clamp capacitor should be high enough to minimize the capacitor ripple voltage, thereby reducing the voltage stress seen by the mosfets. however, a larger clamp capacitor will ultimately result a slower transient response to avoid transformer saturation during load transients. while direct flux limit will automatically limit the pwm on-time only as needed to prevent saturation, a larger clamp capacitor will require a longer time to charge or discharge in response to a load transient. consequently, the value of the clamp capacitor represents a compromise between transient response and mosfet voltage stress. a reasonable value for the clamp capacitor can be calculated using the following: c cl = 1 2l m ? 4 2 f sw ? ? ? ? ? ? 2 an additional design constraint on c cl occurs because of the resonance between the magnetizing inductance l m of the main transformer and the clamp capacitor c cl . if the q of this resonance is too high, it will result in increased voltage stress on the primary-side mosfet during load transients. also, a high q resonance between l m and c cl complicates the compensation of the voltage loop, and can cause oscillations under certain conditions. to avoid the problems associated with this resonance, always use an rc snubber in parallel with the clamp capacitor as shown in figure 9. the values for this rc snubber can then be calculated using: r cs = 1 1? v o v in(min) ? n p n s ? ? ? ? ? ? l m c cl and c cs = 6c cl figure 9 shows a typical arrangement of the active clamp capacitor with an rc snubber. be careful to account for the effect of voltage coefficient for both c cs and c cl to ensure that the above relationship between c cs and c cl is maintained. duty cycle (%) 20 active clamp voltage normalized to 50% duty cycle 1.3 1.4 1.5 1.2 1.1 40 60 30 50 70 80 1.0 0.9 1.6 3766 f08 figure 8. v cl voltage vs duty cycle v in l m swp snubber c cl active clamp pmos c cs 3766 f09 r cs figure 9. active clamp capacitor and snubber direct flux limit in active clamp forward converters, it is essential to es - tablish an accurate limit to the transformer flux density in order to avoid core saturation during load transients or when starting up into a pre-biased output. the l tc3765 and l tc3766 implement a new unique system for moni - toring and directly limiting the flux accumulation in the transformer core. unlike previous methods, the direct flux l i mit directly measures and monitors flux accumulation and guarantees that the transformer will not saturate in either direction, even when starting into a pre-biased output. this technique also provides the best possible transient response, as it will temporarily allow very high duty cycles, only limiting the duty cycle when absolutely necessary. moreover, this technique prevents overcurrent damage to ltc3766 3766fa
24 for more information www.linear.com/ltc3766 a pplica t ions i n f or m a t ion the active clamp pmos, which is a potentially significant weakness in many active clamp forward converter designs. since the direct flux limit functionality is implemented in the ltc3765 on the primary side, there is nothing to adjust on the secondary side. see the ltc3765 data sheet for details on using this feature. note that if the ltc3765 terminates the pg mosfet on-time prematurely to limit flux accumulation, the ltc3766 will sense a premature falling on the sw node. in response, the ltc3766 will automatically terminate the fg on-time, thereby allowing the transformer core to reset. a premature falling on the sw node will also occur whenever the ltc3765 has shut down for any reason. consequently, if the ltc3766 detects 19 consecutive premature sw node falling edges on the sw pin, it will generate a lock fault and shut down. primary-side power mosfet selection on the primary side, the peak-to-peak drive levels for both the n-channel main switch and the p-channel active clamp switch are determined by the voltage on the v cc pin of the ltc3765. this voltage is normally provided through the pulse transformer, and is typically set in the range of 8.5v to 12v. note that even in applications where a logic-level mosfet may be used on the primary side, the v cc voltage on the ltc3765 must still be in this range for proper operation. selection of the n-channel mosfet involves careful consideration of the requirements for breakdown voltage (bv dss ) and maximum drain current, while balancing the losses associated with the on-resistance and parasitic capacitances. in an active clamp topology, the maximum drain voltage seen by this mosfet is approximately: v ds(pg) = 1.2 ? v cl(max) where v cl(max) is the maximum active clamp voltage given above in the active clamp capacitor section. the factor of 1.2 has been added to allow margin for ringing and ripple on the clamp capacitor. it is important to select the lowest possible voltage rating for this mosfet in order to maximize efficiency. note that the rc snubber on the active clamp capacitor (see figure 10) reduces the peak voltage stress on the primary-side mosfet without adding to operating losses. also, the leakage inductance of the main transformer at full load can cause considerable ripple on the active clamp capacitor, pushing up the peak voltage stress seen by the primary-side mosfet. this ripple can be reduced by using a larger active clamp capacitor and a proportionally larger rc snubber capacitor. see active clamp capacitor section for more information. once the required bv dss of the n-channel mosfet is known, choose a mosfet with the lowest available on-resistance (r ds,on ) that has been optimized for switching applications (low q g ). in most applications, the mosfet will be used at a drain current that is a frac - tion of the maximum rated current, so this rating is not normally a consideration. the total losses associated with the n - channel mosfet at maximum output current can be estimated using: p pg = n p n s ? ? ? ? ? ? v out i max ( ) 2 v in 1 + ( ) r ds(on) + n s n p ? ? ? ? ? ? v cl i max r dr q gd f sw 2v miller + q gtot v cc f sw where is the temperature dependence of the on-resistance and v cl is the active clamp voltage (see active clamp ca- pacitor section). r dr (approximately 1.7 for the ltc3765) is the gate drive output resistance at the mosfets miller plateau voltage, v miller . the values of q dg , q gtot and v miller can be taken from the v gs versus q g curve that is typically provided in a mosfet data sheet. q gd is the change in gate charge (q g ) during the region where the v gs voltage is approximately constant and equal to miller voltage, v miller . the total gate charge (q gtot ) is the gate charge when v gs = v cc . the three parts in the above equation represent conduction losses, transition losses and gate drive losses respectively. highest efficiency is obtained by selecting a mosfet that achieves a balance between conduction losses and the sum of transition and gate drive losses. note that the above equation for p pg is an approximation that includes assumptions. first, it is assumed that the turn-on transition losses are rela - tively small because of the leakage inductance in the main transformer. also, it is assumed that the energy stored in this leakage inductance at primar y-switch turn-off is ltc3766 3766fa
25 for more information www.linear.com/ltc3766 a pplica t ions i n f or m a t ion completely recovered by the active clamp capacitor. for most applications, these assumptions are valid and the above equation is a good approximation. the active clamp p-channel mosfet has the same bv dss requirement as that of the n-channel mosfet. since the p-channel mosfet only handles the magnetizing current, it is normally much smaller (typically a sot package). to accommodate abnormal transients, use a p-channel mosfet that has a pulsed drain current rating of 2a or higher. also, note that when the n-channel mosfet turns off, the leakage inductance will momentarily force the re - flected load current into the body diode of the p-channel mosfet . consequently , the body diode should be rated to handle a pulsed forward current of: i d(max) = n s n p ? ? ? ? ? ? i max in some cases, it may be more practical to add a separate diode in parallel with the body diode of the p-channel mosfet. the primary-side p-channel mosfet may be driven by a simple level-shift circuit that shifts down the drive voltage on the ltc3765 ag pin. alternatively, the level-shift circuit can be omitted if the source of the p-channel mosfet is returned to the v cc pin of the ltc3765. refer to the ltc3765 data sheet for details. in nonisolated applications where the ltc3766 is used standalone, it is necessary to use a resonant reset tech - nique instead of the active clamp reset. as a result, there are special considerations in selecting the primar y-side mosfet . see the nonisolated applications section for additional information. secondary-side power mosfet selection on the secondary side, the peak-to-peak drive level for the n-channel mosfets is determined by the v cc pin on the ltc3766. assuming that one or both of the linear regula - tors in the ltc3766 are used, the v cc regulation voltage can be set to either 7v or 8.5v as needed for driving the gates of the mosfets. the first step in selecting the secondary-side mosfets is to determine the needed breakdown voltage. the maximum voltage seen by the synchronous mosfet is approximately: v ds(sg) = 1.2 ? n s n p ? ? ? ? ? ? v in(max) where the factor of 1.2 has been added to allow for ringing and overshoot. this assumes that a snubber has been used on the secondary side of the main transformer (see the rc snubbers section). if no snubber is used, the ringing and peak overshoot will be considerably higher. the maximum voltage seen by the forward mosfet is approximately: v ds(fg) = 1.2 ? v out 1? v out v in(min) n p n s ? ? ? ? ? ? where the factor of 1.2 has again been added to allow for ringing and overshoot. having determined the bv dss requirement for the forward and synchronous mosfets, the next step is to choose the on-resistance. since both secondary-side mosfets are zero-voltage switched, choose mosfets that have a low r ds(on) and have been optimized for use as synchronous rectifiers, including a body diode with a fast reverse re - covery if possible. in most applications, the nominal input voltage will correspond to approximately 50% duty cycle, so the for ward and synchronous mosfet s will be selected to have the same r ds(on) . the power loss associated with the forward mosfet can be approximated by: p fg = n p n s ? ? ? ? ? ? v out i max ( ) 2 v in 1 + ( ) r ds(on) + q gtot v bias f sw where i is the temperature dependence of the on-resistance and v bias is the input to the ltc3766 linear regulator (if used). the value for q gtot can be taken from the v gs versus q g curve given in the mosfet data sheet. q gtot is the value of q g when v gs = v cc , where v cc is the ltc3766 3766fa
26 for more information www.linear.com/ltc3766 a pplica t ions i n f or m a t ion voltage on the v cc pin of the ltc3766. for the synchronous mosfet, the power loss is approximately: p sg = 1? n p n s v out v in ? ? ? ? ? ? i max ( ) 2 1 + ( ) r ds(on) + q gtot v bias f sw the power losses for the synchronous and forward mosfet are generally dominated by conduction losses. for both of the above power loss equations, it is assumed that the dead time (when the mosfet body diode is conducting) has been minimized. see setting the gate drive delays section for details on minimizing the dead time. v cc and drive mode selection in order to accommodate various operating gate voltages that may be required by the secondary-side mosfets, the mode pin can be used to set the ltc3766 for either lv mode or hv mode operation. in lv mode, the v cc regu- lation point for both linear regulators is set to 7v, while the v cc uvlo and v aux switchover rising thresholds are adjusted to 4.7v. in hv mode, the v cc regulation point is set to 8.5v, while the v cc uvlo and the v aux switchover rising thresholds are set to 7.9v and 8v respectively. use lv mode for mosfets that are rated for 4v to 5v opera - tion, and use hv mode for those rated with 7v to 10v operation. the v cc regulation levels, as well as the uvlo and switchover voltages have been optimized to ensure that both types of mosfets are operated safely and ef - ficiently. in general, mosfets with a higher v ds rating also have a higher operating gate voltage rating. as a result, applications with output voltages of approximately 12v and higher will generally use mosfets that are rated for 7v to 10v gate operation. in addition to changing the v cc regulation, uvlo and v aux switchover levels, the selection of hv mode or lv mode also changes the behavior of the sg reverse overcurrent. in lv mode, the reverse overcurrent threshold on the sw pin is 73mv and the adjust current is 103a. in hv mode, these levels are changed to 148mv and 42a to account for the fact that high voltage mosfets have larger on-resistance than low voltage mosfets. for details, see the setting the sg reverse over current. in applications where the ltc3766 is used in conjunction with the ltc3765, the signals on the pt + and pt C pins contain encoded pwm information with amplitude equal to the v cc voltage. this encoded gate drive signal is received by the ltc3765 and decoded into pwm and clock infor - mation that drives the primary-side mosfets. however, the l tc3766 can also be used standalone in nonisolated for ward converter applications. in such applications, the mode pin can be used to disable the pwm encoding on the pt + and pt C pins. as a result, the ltc3766 will generate a normal pwm gate drive signal on the pt + pin and a reference clock on the pt C pin. also, in standalone mode the fgd pin is ignored and the dead time between sg falling and pt + rising is set adaptively. the mode pin has four possible states. tying mode to gnd or v cc will provide encoded gate drive signals with either lv mode or hv mode operation respectively. tying mode to gnd through either a 100k or a 50k resistor will provided standard pwm gate drive signals with either lv mode or hv mode operation respectively. table?3 sum - marizes the use of the mode pin for setting the operat - ing voltage and gate drive encoding modes, and table 4 summarizes the effect of low voltage and high voltage gate drive operating modes. table 3 mode pin drive level pt + /pt C mode intended applications gnd lv encoded pwm low v out isolated apps with ltc3765 v cc hv encoded pwm high v out isolated apps with ltc3765 100k to gnd lv standard pwm low v out , nonisolated apps, standalone 50k to gnd hv standard pwm high v out , nonisolated apps, standalone table 4 drive level v cc v cc uvlo threshold (rise/fall) v aux switchover threshold (rise/fall) sg overcurrent v th i sw lv 7.0v 4.7v/3.9v 4.7v/4.5v 73mv 103a hv 8.5v 7.9v/6.9v 8.0v/7.7v 148mv 42a ltc3766 3766fa
27 for more information www.linear.com/ltc3766 a pplica t ions i n f or m a t ion input capacitor/filter selection in applications with a low impedance source, or where there the input voltage is relatively low, a simple capacitive input filter is generally suitable. this capacitor needs to have a very low esr and must be rated to handle a worst-case rms input current of: i c(rms) = n s n p ? ? ? ? ? ? i out(max) 2 note that capacitor manufacturers ripple current ratings are often based on only 2000 hours of life. this makes it advisable to further derate the capacitor, or to choose a capacitor rated at a higher temperature than required. several capacitors may be paralleled to meet size or height requirements in the design. due to the high operating frequency of the ltc3766, ceramic capacitors can also be used for c in . always consult the manufacturer if there is any question. for higher input voltage applications, however, it can be very costly to use bulk capacitance that is rated to handle the required rms current. also, if a simple capacitor is used as an input filter, it is hard to know exactly where the ac input current will flow when a power supply is placed into a larger system. to avoid these issues, an lc filter can be used on the power supply input as shown in figure 10. this keeps the large ac currents contained in relatively small and inexpensive capacitors whose rms current rating is known to be adequate. choosing an lc filter such that: 1 2 l f c f < f sw 5 will attenuate the ac content of the rms input current by a factor of approximately 5. this greatly alleviates the rms current requirements of the bulk input capacitor. the filter inductor should have a saturation current of at least: i sat(lf) 1.3 ? v out i out(max) v in(min) in order to keep the ripple voltage at the filter output to a reasonable level, choose a value of l f and c f that also satisfies: l f c f < 2.9 ? n s n p ? ? ? ? ? ? v ripple i out(max) + r esr 2 ? ? ? ? ? ? ? ? where v ripple is the desired ripple voltage at the output of the input filter and r esr is the esr of capacitor c f . a reasonable target for v ripple 3% of nominal v in . when using an lc input filter, the output impedance of the lc filter must never be greater in magnitude than the input impedance looking into the power stage of the dc/dc converter. this is necessary to avoid loop insta - bilities. in most applications, this condition is naturally satisfied because the esr of the bulk input capacitance, c bulk , is high enough to lower the q of the lc input filter, thereby reducing the peaking in its output impedance to a safe level. also, using a larger value for c f reduces the q, although this can be expensive in high v in applications. in some situations, a series damping network must be added as shown in figure 10. l f l d v in + v in ? optional c f 3766 f10 z out z in c bulk r d main transformer ? ? figure 10. input filter with optional damping network in order to provide critical damping, choose ld and rd according to: l d = l f 5 andr d = 0.8 l f c f ltc3766 3766fa
28 for more information www.linear.com/ltc3766 a pplica t ions i n f or m a t ion the damping inductor l d does not carry the dc input current. however, to ensure adequate attenuation during large transients, choose an inductor whose saturation current is at least: i sat ld ( ) 0.6 v out i out(max) v in(min) ? ? ? ? ? ? output capacitor selection the selection of c out is driven by the effective series resistance (esr) and the resulting output voltage ripple. typically, once the esr requirement is satisfied, the capacitance is adequate for filtering. the output ripple (?v out ) is approximated by: v out i l esr + 1 8f sw c out ? ? ? ? ? ? where f sw is the operating frequency, c out is the output capacitance and ?i l is the ripple current in the inductor. the output ripple is highest at maximum input voltage since ?i l increases with input voltage. current sensing and average current limit the ltc3766 supports current sensing either with a cur - rent sense resistor or with an isolated current transformer. a current transformer is generally more efficient and has the advantage of sensing current on the primar y side in isolated applications. this can be important because it provides an additional safeguard against saturating the main transformer during load transients. in addition, a current transformer can generate a much larger current sense signal than a sense resistor, resulting in a vastly superior signal to noise ratio. this eases board layout concerns for noise pickup and reduces jitter as well. also, the accuracy of ltc3766 current limit is significantly better in current transformer mode than in current sense mode. compared to a current transformer, a current sense resistor is less expensive and somewhat simpler to apply than a current transformer. when current sensing on the sec - ondary side of an active clamp forward converter, direct flux limit is required to prevent transformer saturation and possible damage of the primary-side mosfet. this is because the current loop does not see the mag - netizing current, and will not provide its own safeguard against saturation. note that in nonisolated applications, however , the current sense resistor is placed in series with the primar y-side switch, so the current loop will be monitoring magnetizing current. when using a current sense resistor, the i s + and i s C pins operate differentially and the maximum peak current thresh - old is approximately 75mv. normally, the current sense resistor is placed in the sour ce of the for ward mosfet, as shown in figure 11. depending on pcb layout and the shielding of the traces going to the i s + and i s C pins, it is sometimes necessary to add a small amount of filtering as shown in figure 11. typically, values of r fl = 100 and c fl = 200pf to 1nf will provide adequate filtering of noise pickup without substantially affecting the current loop response. r fl r fl r sense c fl forward mosfet fg ltc3766 i s ? i s + 3766 f11 figure 11. using a current sense resistor this filter is also helpful in correcting for the effect of the esl (parasitic inductance) of the sense resistor, which can be important for r sense values less than 2m. the effect of the esl is cancelled if the rc filter is chosen so that: r fl c fl = esl r sense since the ltc3766 implements an average current limit architecture, choose the value of r sense based upon the desired average current limit: r sense = 55mv i lim(avg) alternatively, if a current transformer is used to sense the primary-side switch current, then the i s C pin should be tied to v cc and the i s + pin to the output of the current ltc3766 3766fa
29 for more information www.linear.com/ltc3766 a pplica t ions i n f or m a t ion transformer. this causes the gain of the internal current sense amplifier to be reduced, so that the maximum peak current voltage is increased to approximately 1v. the current transformer connections are shown in figure 12. voltage and comparing it to the output inductor current. figure?13 shows an example of a well-calibrated current sense transformer, where the r sense voltage has been scaled by a factor of: sf = n p r sense k ct n s because of the magnetizing current, the slope of the scaled r sense voltage will not exactly match that of the inductor current. choose r cal so that the scaled r sense voltage and the inductor current are identical at the peak. d ct current transformer r cal 1k main transformer n s n p pg v in + v in ? ? ? r sense c fl i s + v cc i s ? 3766 f12 gnd ltc3766 ?? figure 12. using a current sense transformer 20a 500ns/div 3766 f13 inductor current 2a/div sf ? v rsense 2a/div figure 13. properly calibrated current transformer typically, the current transformer is placed in series with the power supply feed to the main transformer. this reduces common mode noise, and is generally convenient for the pcb layout. use a small filter capacitor, c fl , between 1nf and 3.3nf, or a time constant for r sense ? c fl of less than 75ns, to eliminate high frequency noise. the diode d ct is needed to allow the core of the current transformer to properly reset. when using a current transformer, set the value of r sense using: r sense = 0.73v k ct i lim(avg) ? n p n s where n p /n s is the turns ratio of the main transformer, k ct is the current gain of the transformer, and i lim(avg) is the average current limit desired. for most applications, a current transformer turns ratio of 1:100 is suitable (k ct = 0.01). the resistor r cal is added to compensate for the ef- fects of the magnetizing current in the main and current sense transformers, both of which cause the voltage on r sense to be somewhat higher than expected (2% to 8%). typically, r cal is in the range of 1.5k to 5k. for the highest possible accuracy, the value of r cal should be adjusted to calibrate the current sensing at full load and nominal input voltage by carefully measuring the r sense in order to maintain a constant average current while in current limit, the ltc3766 automatically adjusts the value of the peak current limit to cancel the effect of the inductor ripple current. this is accomplished by creating an internal ramp that mimics the inductor current ripple. the amplitude of this ramp is determined by the resistor on the i pk pin, which must be set to be proportional to the output inductor. the ltc3766 establishes a voltage on the i pk pin of (v sw C v s + )/15, which is one-fifteenth of the voltage across the output inductor during the on- time when sw is high. therefore, it is imperative that the sw and v s + pins be connected as shown in figure 14 or figure 15 so that the ltc3766 can properly sense the inductor voltage. if the differential amplifier is not needed, tie v s C and v s + together to v out as shown in figure 14b. for high v out applications where the sw node plateau voltage is greater than 40v, it is necessary to add a resis - tor divider on both the sw and v s + pins, as shown in figure?15. this divider will limit the voltage at the sw pin and also impact the sg reverse overcurrent trip threshold. see setting the sg reverse overcurrent for details on selecting the resistor divider on the sw pin. ltc3766 3766fa
30 for more information www.linear.com/ltc3766 a pplica t ions i n f or m a t ion note that the ratios of the resistor dividers on the sw and v s + pins must be the same for ripple cancellation to operate properly. this requires that: k r = r2 r1 + r2 = 69k ? r4 69k ? r4 + r3 69k + r4 ( ) where the 69k accounts for the internal resistance on the v s + and v s C pins. load current (a) 0 0 output voltage (v) 1 2 3 4 6 5 10 15 20 3766 f16 25 30 5 v in = 72v v in = 36v figure 16. typical current limit performance figure 15. setting r ipk for high v out applications figure 14a. setting the average current limit (r ipk ) figure 14b. setting r ipk with no differential amplifier v s + v s ? r ipk ltc3766 main xfmr v out 3766 f14a v sw v sout v fb sw i pk r b r load r a ? ? v s + v s ? r ipk ltc3766 main xfmr v out 3766 f14 v sw v sout sw i pk ? ? v s ? 160k v s + gnd r ipk ltc3766 main xfmr v out 3766 f15 v sw v sout sw r1 r2 i pk 120k r3 r4 ? ? for resistor sense mode, place a resistor on the i pk pin that is chosen using: r ipk = k r l ipk 17.6nf ( ) r sense where l ipk is the inductance of the output inductor at i = i lim(avg) . for low v out applications where no sw node divider is needed, k r = 1. for current transformer mode, use: r ipk = k r l ipk 1.32nf ( ) k ct r sense ? n p n s when the ltc3766 is in current limit and the output volt - age is very low, the control of the output current will be limited by the minimum on-time of the converter . once this minimum on-time has been reached, further decreases in output voltage during current limit will result in an inductor current that continues to rise, until the over current limit is reached. this will cause the ltc3766 to shut down and attempt a restart, resulting in a hiccup mode of operation. typical average current limit performance is illustrated in figure 16. note that the average current delivered to the load is held substantially constant as the output volt - age is decreased down to a low level, at which point the converter will enter hiccup mode. depending upon the particular application, hiccup mode is entered either due to the loss of secondary-side bias voltage (uvlo) or due to an overcurrent fault. ltc3766 3766fa
31 for more information www.linear.com/ltc3766 a pplica t ions i n f or m a t ion estimating the average current limit accuracy the accuracy of the average current limit depends on the ltc3766 specifications together with a number of applica - tion circuit parameters as well as parasitics. consequently, it is very difficult to precisely calculate the average current limit accuracy . this accuracy can be estimated, however, by carefully considering the three primary sources of error: 1. the accuracy of the current sense resistor and/or cur - rent sense transformer. for resistor sensing, the accu - racy of the current sense resistor is normally 1%. for sense resistors less than 2m, however , the parasitic inductance can cause a significant error in the sensed current. this error can be eliminated by adding an rc filter as shown in figure 11. when using a current transformer, the accuracy of the sense resistor on the current transformer secondar y and the turns ratio of the transformers (both k ct and n p / n s ) are generally 1% or better. depending on where the current sense transformer is placed, however, there can be an additional 1% to 4% error due to the magnetizing current of both the main and current sense transform - ers. generally, this error is in the form of a relatively constant offset, and it can be adjusted out for a particular design for nominal input voltage and maximum load current. the resulting tolerance due to the variation in magnetizing current effects is generally less than 2%, resulting in an overall accuracy of approximately 3% for current transformer sensing. 2. the accuracy of the average current sense threshold v is(avg) . the accuracy of the ltc3766 current sense threshold is given in the electrical characteristics table and depends on the current sense mode chosen. current transformer mode provides an accuracy of 10% and is more accurate than the resistor sense mode accuracy of 15%. 3. the accuracy of the compensation for inductor ripple current. the accuracy of the inductor ripple compensa - tion depends both on the internal adjustment of v ith as well as the tolerance of the output inductor itself. for most application circuits, the ripple compensation accuracy will be 25% or better for current transformer mode, and 35% or better for resistor sense mode. note that the inductor current ripple is typically 30% to 60% of the average current limit, and only one-half of this peak-to-peak ripple is being compensated. as a result, the effect of the ripple compensation accuracy on the average current limit is attenuated by a factor of: f r = r r + 2 where r is the ratio of the peak-to-peak inductor ripple current to the average current limit. for 30% to 60% ripple, for example, the value of f r varies from 0.13 to 0.23. considering each of the above factors, the worst-case tolerance of the average current limit can be estimated as: ?i avg = 3% + 10% + 0.23 (25%) = 18.5% for current transformer mode and: ?i avg = 1% + 15% + 0.23 (35%) = 24% for resistor sense mode. since the three sources of error are statistically independent, the current limit tolerance for current transformer and resistance sense modes can be calculated using the rss method as approximately 12% and 17% respectively. setting the gate drive delays the forward switch gate driver (fg) and the synchronous switch gate driver (sg) operate with make-before-break timing on the fg rising edge, and with simultaneous tim - ing on the sg rising edge. the delays for these transitions relative to the switching of the primar y-side mosfet s are critical for optimizing efficiency, and can be configured independently using the sgd and fgd pins. the sg rising delay should be adjusted to minimize the switch node (sw) body diode conduction. at full load, the power loss in the body diode is significant, and the sg rising delay can have a substantial impact on efficiency. by minimizing the dead time between pg falling and sg rising (while avoiding shoot-through), this power loss is also minimized. similarly, the dead time between sg falling (set by the fg rising delay) and pg rising should also be minimized. ltc3766 3766fa
32 for more information www.linear.com/ltc3766 a pplica t ions i n f or m a t ion in addition to being set to minimize the dead time between sg falling and pg rising, the fg rising delay should also be adjusted to ensure that the drain of the forward switch (swb) is close to 0v when the switch is turned on, which minimizes switching loss. when the ltc3765 active clamp switch turns off, the drain voltage of the primary switch (swp) decreases linearly from v in /(1 C d) to v in , where d is the duty cycle. on the secondary side of the transformer, swb ramps from v out /(1 C d) to 0v. switching power loss is minimized when fg and pg mosfets are switched with minimal drain-to-source voltage across them. the fg and pg rising delays should be adjusted to ensure that the swb and swp nodes are at their minimums when the switches are turned on. keep in mind the following set of relationships when set - ting the delays (refer to the timing diagram and figure 1): 1. the forward gate (fg) always turns on with make- before-break timing relative to the synchronous gate (sg). this ensures that negative inductor current does not create excessive voltage on the synchronous switch drain. 2. shoot-through is caused when the synchronous gate (sg) and the ltc3765 primary gate (pg) are simulta - neously high, or when the forward gate (fg) is high and the l tc3765 active gate (ag) is low . the leakage inductance of the main transformer will prevent signifi - cant power loss due to shoot-through for a few tens of nanoseconds; however, if the pg and sg or fg and ag gates are on simultaneously for a longer period of time, the shoot-through will cause power loss, exces - sive heat, and potentially rapid part displacement. 3. the primary side turn-off of either ag or pg should occur before fg and sg switch, and the primar y-side turn-on should occur after fg and sg switch. for ex - ample, on a particular cycle, ag goes high first (turning the pmos off), then fg goes high, then sg goes low , then pg goes high. on the pg turn-off edge, pg goes low first, then fg goes low and sg goes high, then ag goes low (turning the pmos on). delay resistor selection: pg t urn-off transition in general, the pg turn-off delays are relatively simpler to set and less critical than the pg turn-on delays. at the end of the pwm on-time, the ltc3766 will assert a falling edge on the pt + pin, which in turn causes the ltc3765 to immediately turn off the pg mosfet. after a fixed 180ns delay, the ltc3765 will then turn on the ag mosfet. consequently, the only delay adjustment to be made for this transition is on the secondary side using the sgd pin of the ltc3766. this pin is used to set the delay from pt + falling to fg falling/sg rising, which must occur after pg turn-off and before ag turn-on. the first consideration in setting the sgd delay is to reduce the dead time between pg and sg, during which the body diode of the synchronous mosfet is carrying the load current. after pg turn-off, the sw node on the secondary side will rapidly fall until being clamped by the body diode of the sg mosfet. the objective is to turn on the sg mosfet as the sw node crosses through 0v. the ltc3766 makes this easy to achieve by directly sensing the sw node and inhibiting sg turn-on until sw has fallen through 0.5v. in other words, minimum dead time between pg and sg can be achieved by setting the sgd delay to any value less than or equal to the delay time from pt + falling to sw falling through 0v. in general, this delay time is in the range of 50ns to 100ns. the resistor from sgd to ground that gives a particular delay t sgd can be computed using: r sgd = t sgd ? 12ns ( ) ? 1k 4.3ns a 10k resistor from sgd to ground sets the fg falling/sg rising delay to approximately 50ns, which is generally a good starting point. to prevent damaging cross conduc - tion between the fg and ag mosfets, do not set the sgd delay to be longer than the 180ns fixed turn-on delay of the ag mosfet . always start low when setting the sgd delay. this is safe because of the adaptive limit that inhibits premature sg turn-on. ltc3766 3766fa
33 for more information www.linear.com/ltc3766 a pplica t ions i n f or m a t ion another important consideration in setting the sgd delay is the prevention of swp collapse due to excessive fg turn-off delay. after pg turn-off, the swp node is quickly driven high by the transformer leakage to a level of ap - proximately v in /(1 C d). ideally, it should remain at this voltage as fg turns off, sg turns on, and then ag turns on. however, if the delay to fg turn-off is too long, the swp voltage will momentarily fall towards v in , and it will not rise again until being forced high by ag turn-on. this collapse of the swp node is illustrated in figure 17, and is more prominent at lighter loads. it can significantly degrade efficiency as the swp node is discharged and recharged every cycle, but it is easily avoided by further shortening the sgd delay. although the ltc3766 inhibits the sg turn-on until sw < 0.5v, this is not true of the delay to fg turn-off. the delay from pt + falling to fg turn-off can be decreased beyond the adaptive limit of sg turn-on, so that the fg and sg edges can be separated with a small dead time between them. this is important to allow the fg turn-off to be separately opti - mized based upon circuit parasitics. in most applications, a peak in full load efficiency is normally found with the sgd delay set so that there is no swp collapse and there is a small dead time between fg turn-off and sg turn-on. in applications where efficiency is less critical, this delay can be set adaptively by tying sgd to gnd. in this case, fg falling and sg rising will both be inhibited until sw < 0.5v. for fixed delay mode, always use a resistor of 8k or greater on the sgd pin to avoid activating the adaptive delay mode. delay resistor selection: pg t urn-on transition the delays associated with the pg turn-on transition are set by the delay pin on the ltc3765 and the fgd pin on the ltc3766. at the beginning of the pwm on-time, the ltc3766 will assert the pt + pin high, and will then turn fg on and sg off after a delay set by the resistor on the fgd pin. on the primary side, the ltc3765 will immediately turn off the ag mosfet in response to pt + rising, and it will then turn on the pg mosfet after a delay determined by the resistor on the ltc3765 delay pin. the fgd delay resistor on the secondary side must be selected in careful coordination with the delay on the primary side; therefore, the following procedure outlines how to choose compo - nents for both the ltc3765 and ltc3766. the first objective in setting the pg turn-on delays is to minimize switching loss by turning on the pg and fg mosfets at minimum drain voltage. after the ag mosfet has turned off, the pg and fg drain voltages (swp and swb) will naturally ramp down to approximately v in and 0v respectively. these voltages take 100ns to 500ns or longer to fall, depending on the main transformer mag - netizing inductance and the parasitic capacitance on the mosfet drains. choosing the delay settings correctly can significantly impact the power loss due to switching the mosfets. for a particular design, the most effective procedure is to set the pg and fg delays based on the resulting waveform on swp and swb. in order to evaluate these waveforms, v in 1 ? d ~ v in 1 ? d ~ v in swp node swp node ag pt + fg ag pt + fg t sgd too long 0v v in 0v t sgd ok 3766 f17 figure 17. avoiding swp collapse from long delay ltc3766 3766fa
34 for more information www.linear.com/ltc3766 a pplica t ions i n f or m a t ion the delays should initially be selected so that they are long, while keeping in mind that the fg delay must be less than the pg delay to prevent potentially damaging pg/sg cross-conduction. as a first pass, use a 75k resistor from fgd to ground for a 415ns delay and 60k resistor from delay to ground for a 622ns delay. the swp and swb waveforms should appear as shown in figure 18. the ramp rate on swb and swp is to a first order inde - pendent of duty cycle; however, the starting point of the ramp is a function of the duty cycle. therefore, the longest delay time will be at high duty cycle when v in is at a mini - mum. for the lowest switching losses over the range of input voltage, the delays should be chosen based on the waveforms when v in is at its minimum operating voltage. the resistor value from the fgd pin to ground should be selected first. this should be chosen to give a delay equal to the time from pt + rising until swb ramps down to ap - proximately 0v. the fgd resistor value can be determined from the following equation: r fgd = t fgd ? 18ns ( ) ? 1k 5.1ns note that if the fg turns on before the swp and swb voltages have naturally fallen to their minimums, they will be instantly pulled to their minimum by the fg mosfet turning on. this can give the appearance that fg is turn - ing on after swb has ramped to 0v, although it is actually premature. t urning on fg prematurely will slightly degrade efficiency due to increased switching loss; however, if the fall time of swp and swb exceed a maximum fgd delay of 600ns, it is acceptable to have premature fg turn-on at low input voltage. generally, the delay will be adequate at higher v in to allow a complete ramp down. in rare cases, the ltc3765 and ltc3766 will be in delay phase-out mode when operating at minimum v in voltage. this will be apparent because the measured delay will be smaller than the programmed delay on either or both chips. this feature allows the ltc3765 and ltc3766 to operate at duty cycles up to a maximum of 79% by reducing the programmed delays when they would otherwise limit the maximum duty cycle. if this mode is evident, increase v in until delay phase-out is no longer active, and then set the fgd delay as described above. having set the fgd delay to optimize for low voltage switching, the pg delay is next chosen to minimize the dead time between sg turn-off and pg turn-on. the delay for the primary gate can be determined by taking the de - lay set tolerance and rise/fall times into account. the fg delay setting on the ltc3766 and the pg delay setting on the l tc3765 are both accurate to within 15% for a range of resistance values. given this accuracy, a reasonable choice for the ltc3765 delay time is to set the pg delay time to 1.22 ? t fgd . be aware that the fall time of sg and the rise time of pg cannot be neglected. for example, if sg is driving a mosfet with high input capacitance, and pg is driving a mosfet with low input capacitance, then sg will fall slowly and pg will rise quickly. this increases the potential for shoot- through. moreover, since sg will not turn off until fg turns on (make before break), the rise time of fg is also a factor. a final consideration is that the ltc3765 experiences a delay in pt + rising due to the pulse transformer. all of these considerations can be accounted for in the delay resistor selection by the following equation, in which t d(pt) is the delay time from pt + rising to in + rising on the ltc3765, t r(fg) is the rise time of fg to 2v, t f(sg) is the fall time of v in 1 ? d ~ v out 1 ? d ~ v in swp node swb node pt + 0v 0v 0v t fgd 3766 f18 figure 18. swp and swb waveforms ltc3766 3766fa
35 for more information www.linear.com/ltc3766 a pplica t ions i n f or m a t ion sg to 1v and t r(pg) is the rise time of pg to 1v. the delay time can then be chosen such that: t pgd = 1.22 ? t fgd + t r(fg) + t f(sg) C t r(pg) C t d(pt) the resistor from the ltc3765 delay pin to ground can be selected to give this delay by using the following equation: r delay = t pgd ? 45ns ( ) ? 1k 9.5ns in practice, the ltc3765 pg turn-on delay should be optimized by monitoring the pg and sg waveforms. a conservative approach is to set the pg delay to create a dead time between sg falling and pg rising that accounts for the delay set tolerances (typically 22% of the total delay). a more aggressive approach takes into account the fact that transformer leakage inductance will delay the effect of pg turn on (i.e., sw node rising) by 75ns to 150ns or more at full load. also, transformer leakage inductance mitigates the effect of a small amount of shoot-through by slowing the rise time of the transformer current. higher full-load efficiency can be achieved by setting the pg turn- on closer to sg turn-off. in addition, a shorter dead time at pg turn-on can reduce the overshoot and ringing on the switch node, thereby reducing the size of the required rc snubber and its associated power loss. while a shorter dead time at pg turn on can improve full-load performance, care must be taken to ensure that the worst case shoot-through at no load is well within safe limits. maximum duty cycle and delay phase-out while the pg turn-on delay time is important for reducing turn-on switching losses, no power is transferred from the input supply to the output load during this delay time. in most forward converter systems, the maximum available duty cycle is artificially limited by this delay, which then forces a trade-off between the optimal delay time and the maximum available duty cycle. the ltc3765 and ltc3766 implement a unique delay phase-out feature in which the pg and fg turn-on delays are gradually reduced as the demanded duty cycle approaches the maximum value of 79%. this feature allows a forward converter to be designed with an optimal delay at nominal input voltage, but still approach the maximum duty cycle at low input voltage, thereby making better utilization of the power transformer. generating secondary-side bias there are five items to consider when determining the best way to generate bias for the ltc3766 in an isolated application: 1. the required operating current. this includes the gate drive current for both primary and secondar y mosfets as well as the operating supply currents of both the ltc3765 and the ltc3766. 2. the operating voltage needed for the mosfet gates. depending on whether logic-level or standard thresh - old mosfets are used, the v cc operating voltage and undervoltage lockout (uvlo) levels can be set accord - ingly using the mode pin. the bias supply must provide adequate voltage to keep the l tc3766 v cc pin above its uvlo level and keep the overall supply operating at peak efficiency. 3. current limit operation at low output voltage. the minimum required v out during current limit relative to the normal operating v out has a major impact on the design of the bias supply. the bias supply must provide adequate voltage over this range of v out voltages. 4. the variation in input voltage. at minimum input voltage, the bias supply must still provide enough voltage for proper operation. at maximum voltage, the bias supply must not generate a voltage that exceeds maximum ratings or dissipates excessive power . 5. the potential need for a rapid hand-off from primary to secondar y control. in polyphase applications, it is important to quickly transfer control to the secondary side during start-up so that current sharing and proper phasing can be established before the full load current is seen at the output. by contrast, some applications may not need to have control handed off to the second - ary until just prior to the output reaching its regulation value. in all applications, however , the secondary bias must always come up and control must be transferred before the output reaches the regulation level. the current that must be supplied by the secondary bias supply can be estimated using i vcc (q gpri f sw + 3ma)n pt + q gsec f sw + 18ma ltc3766 3766fa
36 for more information www.linear.com/ltc3766 a pplica t ions i n f or m a t ion where q gpri is the total gate charge of all primary-side mosfets, q gsec is the total gate charge of all secondary- side mosfets, and n pt is the turns ratio of the pulse transformer. note that the primary-side current is scaled by the turns ratio of the pulse transformer. the 18ma constant in the above equation includes typical gate drive switching current as well as losses associated with the pulse transformer. using v out directly for secondary-side bias the simplest method of generating secondary-side bias is to directly use the output voltage of the converter. this is only practical when v out is in the range of 5v to 15v. when v out is in the range of 5v to 10v, it can be directly connected to v cc as shown in figure 4a. when v out is in the range of 6v to 15v, it can be used as a bias input to the v aux regulator as shown in figure 4b. for output voltages higher than 15v, this method is generally not practical due to high power dissipation. this simple method also does not provide constant current limit operation at lower output voltage. it also does not provide a quick hand-off to the secondary and is not recommended for polyphase applications. using a peak charge circuit for secondary-side bias a common way to generate a bias voltage on the second - ary side is by using a peak charge circuit connected to the transformer secondar y, as shown in figure 19. this circuit is useful for generating an unregulated bias voltage that can be directly tied to the v in pin of the chip and used as an input to the high voltage linear regulator. the peak charge circuit is capable of providing bias even at low output voltages, so it is a good choice when constant current limit operation is needed over a wide v out range. since it provides a bias voltage even when the converter is operating at tiny duty cycles, the peak charge is also a good choice for polyphase applications where a quick hand-off to secondary is important. however, since the output of a peak charge circuit directly follows changes in the converter input voltage, it is should only be used in applications where the input voltage varies by 2:1 or less. note that for bias voltages on the v in pin of 28v or greater, the internal 30v clamp will draw between 3.5ma and 7ma. this will result in 100mw to 200mw of additional power dissipation in the ltc3766. to limit the initial charging current out of the peak charge circuit, use a series resis - tor r pk in the range of 1 to 4. a schottky diode d pk with a peak surge current rating of 5a or higher should also be used, and the pass transistor q1 should have a minimum beta of at least 200. capacitor c pk should be a ceramic capacitor with a value of at least 2.2f or greater. during open-loop start-up, it is imperative that the peak charge bias come up and control is transferred to the secondary before an output overvoltage can occur. since a peak charge circuit is not directly coupled to the output voltage of the converter, care must be taken to ensure that the primary-side soft-start is not too fast relative to the rise time of the peak charge bias on the secondary side. the time required for the peak charge bias voltage to rise to a level that allows control to be handed off to the secondary can be approximated using: t bias 10 3 ? r eq c pk c ssp + 150s where r eq is the sum of r pk and the series resistance of diode d pk , and c ssp is the ltc3765 soft-start capacitor. during open-loop soft-start, the time required for the converter output voltage to reach a given level v ho can be approximated using t out 10 4 ? c ssp 2 v ho ( ) 2 lc out f sw v in(min) ? n s n p ? ? ? ? ? ? 2 ? ? ? ? ? ? ? ? ? ? ? ? ? ? 1/3 the above equation assumes that there is no load current, which is the worst-case condition for output voltage rise. v in from transformer secondary r pk d pk c vcc ndrv ltc3766 v bias = 6v to 32v v cc c pk q1 3766 f19 figure 19. peak charge circuit for secondary bias ltc3766 3766fa
37 for more information www.linear.com/ltc3766 a pplica t ions i n f or m a t ion when calculating t out , use a value for v ho that corre- sponds to the target output voltage for control hand-off, ty pi cally one-half the normal regulation level or less. if t out is less than t bias , then the ltc3765 soft-start capacitor value should be increased. note that these equations are approximations and the actual times will vary somewhat with circuit parameters. peak charge bias configurations when the peak voltage on the sw node is in the range of 7v to 32v, the peak charge can be taken directly from the sw node as shown in figure 20. in practice, this condi - tion only holds when the output voltage of the converter is approximately 5v . in most applications, it is necessar y to add an additional auxiliary winding on the secondary for use in generating an adequate bias voltage. for low v out applications (v out < 5v), this winding can be configured as shown in figure?21 to provide a higher voltage for bias generation. this configuration is advantageous because it achieves a higher voltage on the transformer secondary with a minimum number of additional turns. the number of turns on the auxiliary winding for this configuration should be approximately: n aux n s v b(min) d max v out ? 1 ? ? ? ? ? ? where d max is the maximum operating duty cycle (typically 0.65 to 0.70) and v b(min) is either 7v for low voltage or 10v for high voltage drive mode operation. these values for v b(min) are approximately 2v higher than the uvlo levels on the ltc3766 to allow for drops in the peak charge circuit. as an example, for v out = 1.5v, d max = 0.65v and n s = 1 turn, use n aux = 2 turns, assuming low voltage drive mode. for high v out applications (v out > 6v), this winding can be configured as shown in figure 22 to provide a reduced voltage for generating bias. in this case, choose an auxiliary winding with turns n aux n s v b(min) d max v out ? ? ? ? ? ? v in r pk d pk sw n s n p c vcc 3766 f20 ndrv ltc3766 main xfmr v bias = 6v to 32v v cc c pk q1 ?? figure 20. peak charge directly from sw for v out 5v v in r pk d pk n s n aux sw n p c vcc 3766 f21 ndrv ltc3766 main xfmr v bias = 6v to 32v v cc c pk q1 ? ? ? figure 21. peak charge for low v out applications v in r pk d pk n s n aux sw n p c vcc 3766 f22 ndrv ltc3766 main xfmr v bias = 6v to 32v v cc c pk q1 ? ? ? figure 22. peak charge for high v out applications ltc3766 3766fa
38 for more information www.linear.com/ltc3766 a pplica t ions i n f or m a t ion at maximum v in , there may be considerable power dis - sipation in the linear regulator pass device q1. this power can be calculated using p q1 = (v bias C v cc )i vcc in applications where the peak charge and high voltage linear regulator must operate continuously, transistor q1 must be capable of dissipating this power without excessive temperature rise. in such applications, use a transistor with a suitable package (sot89) and connect the thermal tab of the transistor to an adequately large island of copper on the pcb. high efficiency secondary-side bias techniques a high-efficiency alternative to using a peak-charge circuit to generate secondary-side bias is to connect a buck output to the transformer secondary. this buck output is normally combined with a peak charge circuit as shown in figures?23 and 24. the bias voltage from this buck output can be fed directly into the v aux pin. this arrangement combines the quick start-up and flexibility of a peak charge circuit with the higher operating efficiency of a buck bias supply. for figure 23, the output voltage of the buck bias supply is given by: v buck = v out 1 + n aux n s ? ? ? ? ? ? ? 0.5 for figure 24 the output is given by: v buck = v out n aux n s ? 0.5 for a buck bias supply, inductor l bk must be rated to carry the required v cc bias current and should have an inductance value that will provide continuous current operation at one-fourth of the required bias current load or less. choose and inductor l bk to according to: l bk > v cc i cc f sw a value of 1mh for l bk is adequate for most applications. the output voltage of the buck bias supply (v buck ) should be set to optimize efficiency during normal operation. this will typically require a somewhat higher number of auxiliary turns than is ideal for a peak charge output. as a result, the buck supply and the peak charge circuit are sometimes driven from separate auxiliary windings. also, note that the output voltage of the peak charge circuit will increase somewhat when the v aux bypass regulator is activated and the high voltage linear regulator is disabled. care must be taken not to exceed the maximum voltage rating on the v in pin of the ltc3766. figure 23. buck bias supply for low v out applications figure 24. buck bias supply for high v out applications v in v aux regsd r pk d pk n s n aux sw n p c vcc 3766 f23 ndrv ltc3766 option to limit q1 power main xfmr v bias = 6v to 32v v cc d bk l bk d bk c pk c rsd c bk v buck q1 ? ? ? v in v aux regsd r pk d pk n s n aux sw n p c vcc 3766 f24 ndrv ltc3766 option to limit q1 power main xfmr v bias = 6v to 32v v cc d bk l bk d bk c pk c rsd c bk v buck q1 ? ? ? ltc3766 3766fa
39 for more information www.linear.com/ltc3766 a pplica t ions i n f or m a t ion the buck bias winding can also be used standalone without the peak charge supply, as shown in figure 25. this is sometimes done in applications where the peak charge circuit is impractical, such when the v in voltage has a wide range. when using the buck bias supply standalone, particular care must be taken to ensure that the bias output comes up more quickly than the main output, and that there is adequate bias voltage immediately after control hand- off. this is made more difficult by the presence of some load on the v cc pin during start-up whereas there may be no load on the main output. in general, a clean start- up with a standalone buck bias supply can be achieved by observing the following guidelines: 1) set the turns ratio of the auxiliary winding so that the operating v aux will be at least 3v above the rising v cc uvlo voltage, 2) use a smaller value for l bk , typically one-half of that calculated in the above equation, but always large enough for continuous current in l bk during normal operation 3) use the high-voltage linear regulator to minimize the load on v cc during start-up, 4) use the run pin to monitor the bias voltage and set the start-up voltage to 2v above the rising v cc uvlo voltage with a hysteresis of 1.5v, 5) use a shorter soft-start time, less than 10ms if possible, 6) use a small v cc capacitor (typically c vcc = 0.22f) and a capacitor c bk given by: c bk = 20 q gpri f sw + 3ma ( ) n pt + 18ma ? ? ? ? f sw v hyst where v hyst is the hysteresis set by the run pin (1.5v). note that this value for c bk is as small as possible so that v buck rises quickly, but large enough to support the bias current until control is handed off to the secondary and the duty cycle increases. once control is handed off, both the buck supply and the main converter will be operating in continuous current mode, so their outputs will track. another high efficiency option for generating bias is to make use of an inductor overwinding, as shown in figure?26. this supply is created by adding a second winding on the main output inductor. during the on-time of the synchronous mosfet, the v out voltage is scaled and coupled through diode d ow to capaci - tor c ow , so that the resulting bias voltage is: v ow = v out n l2 n l1 ? 0.5 this is similar to the buck supply in that it is highly efficient and fairly well regulated. however, it is simpler in that it does not require the use of an additional inductor to gener - ate the bias voltage. another advantage of this technique is that the bias voltage always tracks v out , so there is no concern about the bias voltage potentially lagging the output voltage during start-up. like the buck bias supply, the inductor overwinding can be used either stand alone (as shown in figure 26) or together with a peak charge bias supply. use a schottky diode d ow with a peak surge current rating of 5a or higher. capacitor c ow should be a ceramic capacitor with a value of 2.2f or greater. v in v buck run r r2 d bk d bk l bk c vcc ndrv ltc3766 v cc r r1 c bk q1 3766 f25 n p n aux main xfmr ?? figure 25. using the buck bias supply standalone v in v aux ndrv ltc3766 v cc c vcc 3766 f26 c ow d ow n l2 sw main xfmr n l1 n s n p v ow c out v out ? ? figure 26. inductor overwinding bias supply ltc3766 3766fa
40 for more information www.linear.com/ltc3766 a pplica t ions i n f or m a t ion a useful variant of the inductor over-winding bias supply is shown in figure 27, where a discrete transformer t ow has been used instead of an additional winding on the main inductor l f . this is often more convenient because standard parts can readily be used. in the circuit of figure 27, a second diode d ow2 has been added to prevent dc bias current from being carried in the transformer t ow . this transformer can be either a gate-drive or flyback-style transformer, which are widely available in a range of turns ratios. note that transformer t ow requires only functional isolation and can be physically very small. this circuit produces a bias voltage given by: v ow = v out ? 0.5 ( ) n l2 n l1 ? 0.5 during an output overload condition, the voltage generated by a either a buck supply or inductor overwinding sup - ply will drop as the converter output voltage decreases. if this happens and there is no peak charge bias supply , then the l tc3766 will have a uvlo fault that will cause both the ltc3765 and ltc3766 to shut down and attempt a restart. if a peak charge supply is used together with a buck or inductor overwinding supply, then the ltc3766 will automatically re-energize the high voltage linear regulator when the v aux pin gets too low. if continuous operation of the peak charge and high voltage regulator is not needed, then the regsd pin can be used to limit the total time that this regulator is allowed to operate (shown as an option in figures 23 and 24). this enables a low power pass transistor to be used. see linear regulator operation for more information on using the regsd feature. soft-start ramp time and control hand-off the soft-start ramp time on the ltc3766 is set by placing a capacitor between the ss pin and gnd. this secondary-side soft-start capacitor only controls the output voltage ramp after control hand-off has taken place. consequently, its effect on the overall output voltage start-up will depend on the primary to secondary hand-off voltage in the particular application. choose a soft-start capacitor using: c ss = 5a ( ) t ss 1.83 0.6 ? v fb(ho) ( ) where t ss is the soft-start time after control hand-off to the secondary and v fb(ho) is the voltage on the fb pin at control hand-off. the total soft-start time will be the sum of t ss and the open-loop soft-start time prior to control hand-off set by the ltc3765. note that during the open- loop soft-start time, the output voltage ramp will vary significantly with load, since the synchronous mosfet is not enabled and the converter may operate in discontinu - ous current mode. if precise control over the soft-start time is desired, use a secondar y-side bias scheme that provides control hand-off at the lowest possible output voltage. see above sections on generating secondar y-side bias for details. just prior to control hand-off, the ltc3766 rapidly pre - sets the soft-start capacitor so that the internal soft-start voltage is equal to v fb(ho) , ensuring a smooth transition from primary to secondary control. due to the dielectric absorption of the soft-start capacitor, however, the voltage on the soft-start capacitor may droop somewhat following the initial preset. this can result in a small step down in the output voltage ramp after control hand-off, and an associ - ated negative current transient in the output inductor. to minimize this effect, use a soft-start capacitor with a low dielectric absorption, such as an npo ceramic capacitor. pulse t ransformer selection the pulse transformer that connects the ltc3766 pt + /pt ? outputs to the ltc3765 in + /in ? inputs functions v in v aux ndrv ltc3766 v cc c vcc 3766 f27 c ow d ow1 d ow2 n l2 sw main xfmr n l1 l f n s n p v ow c out v out ? ? figure 27. inductor overwinding using standard parts ltc3766 3766fa
41 for more information www.linear.com/ltc3766 a pplica t ions i n f or m a t ion as the communication link between the secondary-side controller and the primary-side gate driver, as shown in figure 28. in addition, ltc3765 contains a bridge recti - fier that extracts bias power from the pulse transformer, wh ich it then uses to drive the gates of the primary-side mosfets. the designs have been coordinated so that the transformer turns ratio should be set to: n pt = n ltc3765 : n ltc3766 = 2:1 for low voltage mode operation on the ltc3766 (v cc = 7v), and: n pt = n ltc3765 : n ltc3766 = 1.5:1 for high voltage mode operation on the ltc3766 (v cc = 8.5v). the resulting v cc voltage on the ltc3765 is approximately: v cc(3765) = v cc(3766) n pt C 1.3 using the above turns ratios will provide a primary-side v cc voltage of approximately 12v for the ltc3765 to drive the gates of the primary-side mosfet. note that the primary-side v cc voltage provided by the pulse transformer must also be greater than the ltc3765 uvlo threshold for proper operation. care must also be taken not to exceed the maximum voltage rating on the ltc3765 v cc pin. the pulse transformer must also have a minimum volt- second rating as required by the 79% duty cycle signal on pt + /pt ? and the lowest frequency of operation. the required volt-seconds rating can be calculated from the minimum frequency as: volt-sec = 0.33 ? v cc f sw(min) since the pulse transformer is used for transmitting pwm information as well as bias power, choose a pulse transformer with a leakage inductance of 1h or less. this reduces ringing and distortion of the pwm information so that a solid communication link is always maintained. for low voltage (7v) mode on the ltc3766, transformers that meet the above requirements include the pa2008 from pulse engineering and the da2320 from coilcraft. for high voltage (8.5v) mode on the ltc3766, transformers that meet the above requirements include the pa3290 from pulse engineering. the 1f and 0.1f capacitors in series with the pulse transformer of figure 28 are for blocking and restoring the dc level of the signal. the 220pf/100 rc snubber shown at the in + /in C inputs of the ltc3765 is required to minimize ringing due to the leakage inductance of the pulse transformer. the values shown for each of these four components are appropriate in nearly all ltc3765/ ltc3766 applications. voltage loop compensation the voltage loop of the ltc3766 is compensated in much the same way as a standard buck converter, by placing a compensation network on the ith pin. it is important to note, however, that the speed and stability of the voltage loop is heavily dependent upon several factors apart from the design of the ith compensation. common pcb layout errors, for example, often appear as stability problems. examples include the distant placement of the input de - coupling capacitor, connecting the ith compensation to a ground track carr ying significant switch current, and rout - ing the fb signal over a long distance such that noise pick occurs. refer to the pcb checklist section for additional information. another factor that affects the voltage loop is the choice of output capacitor. if the value is too low, or the esr is too high, then it will not be possible to achieve optimum loop performance. a third factor that can impair loop response is the presence of underdamped resonances in the power stage. examples include an underdamped lc input filter or an active clamp capacitor resonating with the main transformer magnetizing inductance. refer to the input capacitor/filter selection and active clamp capacitor sections for details on how to properly damp these lc resonances. before attempting to optimize the loop response, carefully consider the above factors, in + in ? 100 0.1f n ltc3765 :n ltc3766 220pf 3766 f28 ltc3765 pt + pt ? ltc3766 1f ?? figure 28. pulse transformer connection ltc3766 3766fa
42 for more information www.linear.com/ltc3766 a pplica t ions i n f or m a t ion because no amount of tweaking to the ith components can cancel their effect. also, any theoretical analysis of loop response only considers first order non-ideal component behavior. consequently, it is important that a final stability check be made with production layout and components. stabilizing the voltage loop of the ltc3766 is accomplished by using the error amp to provide a gain from v out to ith that compensates for the control to output gain from ith to v out . the dc component of the ith to v out gain is approximately: a dc1 = 1 29.3r sense ? 2lf sw r out 2lf sw + r out for resistor sense mode, and: a dc1 = n p 2.2k ct n s r sense ? 2lf sw r out 2lf sw + r out for current transformer mode. since the ltc3766 utilizes current mode control, the ith to v out transfer function can be basically characterized by one pole and one zero. the pole is given approximately by: f p = 1 2 r out c + 1 f sw lc and the zero is given by: f z = 1 2 r esr c where r esr is the esr of the output capacitance c. note that the frequency of this zero will vary substantially de - pending on the type of capacitor chosen. the l tc3766 uses i nternal slope compensation to stabilize the current loop. the amount of slope that is effectively seen at the current sense (i s + ) input is: s r = kf sw (26mv) for r sense mode and: s r = kf sw (0.35v) for current transformer mode, where k = 1 for duty cycles less than 50% and k = 2 for duty cycles greater than 50%. for most applications, this internal slope compensation will be on the order of the down slope of the inductor, which provides adequate current-loop stability without introduc - ing excessive phase shift at the crossover frequency. for phase margin calculations, assume that two poles exist at one-half of the switching frequency . use of an abnor - mally high valued inductor will produce additional phase shift due to slope compensation, thereby forcing a lower voltage loop crossover frequency to ensure stability . in order to avoid having either too little or too much slope compensation, make sure that the inductor satisfies the following inequalities: 2v out r sense 3s r@k = 2 < l < 3v out r sense s r@k = 1 for resistor sense mode and: 2v out r sense k ct n s 3s r@k = 2 n p < l < 3v out r sense k ct n s s r@k = 1 n p for current transformer mode. in some cases, the ltc3766 and ltc3765 will be in delay phase-out mode at low input voltages. this cycle-by-cycle reduction of the pg and fg turn-on delays has the effect of reducing the amount of slope compensation by ap - proximately 20% to 40%. consequently, a higher value of inductance may be required to maintain current-loop stability during operation in delay phase-out mode. the compensation network is typically configured as shown in figure 29. the objective of this network is to add dc gain for excellent load regulation while providing good phase margin in the voltage loop at the highest possible crossover frequency. normally this is achieved by adding a dominant pole at very low frequency and a zero well be - fore the crossover frequency to remove most of the phase figure 29. ith compensation network 0.6v fb ith r1 r3 r2 v out c1 3766 f29 c2 c3 (opt) g m = 2.7ms ltc3766 + ? ea ltc3766 3766fa
43 for more information www.linear.com/ltc3766 a pplica t ions i n f or m a t ion associated with the dominant pole. a high frequency pole is also added to reduce noise and provide attenuation of the output voltage ripple. note that significant gain at the switching frequency in this compensation network can cause instabilities. the network of figure 29 has a dc gain of: a dc2 = r2 r2 + r3 g m r ea where r ea = 5m is the output resistance of the error amplifier and g m = 2.7ms is the transconductance. the low frequency pole and zero are given by: f p1 = 1 2 r ea c3 andf z1 = 1 2 r1c1 and the high frequency pole is given by: f p2 = 1 2 r1c2 a good target for the 0db crossover frequency of the voltage loop is between one-tenth and one-fifth of the switching frequency and a phase margin of 60 or more. note that the zero produced by the esr of the output capacitor helps to stabilize the loop by providing positive phase shift at frequencies near crossover. this tends to cancel the negative phase shift associated with the high frequency current loop poles. however, if the output capacitor is purely ceramic, the esr zero may be at too high a frequency to contribute phase lead to the overall loop response. in this case, it can be helpful to add an optional phase lead capacitor c3 as shown in figure 29, which generates a zero at a frequency of: f z2 = 1 2 r3c3 this zero should be placed near the crossover frequency to provide additional phase boost. when optimizing the voltage loop, bear in mind that the large signal step response may be limited by factors other than the crossover frequency. at low input voltage, for example, the maximum duty cycle limit of 79% will impair the ability of the loop to respond to a sudden increase in load. also, in responding to a very large load step (e.g., zero to full load) the loop may demand duty cycles that cause the main transformer to saturate. hard saturation is prevented if current in sensed on the primary side or if the volt-second clamp is used, but the large signal step response will be limited by the available excess volt- seconds in the main transformer. setting the sg reverse overcurrent the ltc3766 has been carefully designed to turn off the sg mosfet as needed to prevent an overcurrent during start-up, shutdown and normal operation. nevertheless, the ltc3766 also contains a user-adjustable sg reverse- overcurrent protection circuit as an added protection feature. this feature is also useful in special applications where it may be advantageous to limit the sg reverse current to a particular value. sg reverse overcurrent is implemented by monitoring the voltage on the sw pin when sg is high, and terminating the sg on-time for the duration of the switching cycle if the sw voltage exceeds an internal threshold. if the ltc3766 is operating at zero duty cycle when the sg overcurrent occurs, then the fg mosfet is forced on prior to sg turn-off to re-route cur - rent to the primary and prevent avalanche from occurring. if not adjusted, the internal sg overcurrent threshold has been set high enough so that it should not interfere with the operation of normal applications. be careful to make kelvin connections from sw and gnd to the drain and source of the sg mosfet. in addition to a fixed internal threshold on the sw pin, a current is sourced from the sw pin so that a resistor can be added to decrease the overcurrent threshold if desired. both the sw pin threshold and the adjust current are changed depending on whether the ltc3766 is operating in hv or lv mode, so as to account for the higher on-resistance of high voltage mosfets. in applications where the sw node plateau voltage is 40v or less (v in ? n s /n p 40), a single resistor can be used to set the sg overcurrent threshold (figure 30). the resulting overcurrent v ds on the sg mosfet is given by: v oc = v rev C i rev r sw ltc3766 3766fa
44 for more information www.linear.com/ltc3766 a pplica t ions i n f or m a t ion the sg overcurrent trip should normally be targeted at twice the maximum v ds of the sg mosfet during normal operation. this can be estimated using: v oc = r ds(max) v out f sw l 1? v out v in(max) ? n p n s ? ? ? ? ? ? where r ds(max) is the maximum r ds(on) of the sg mosfet over temperature. this equation allows for twice the reverse sg current that would normally occur due to the inductor current ripple at no load. the % error in the sg overcurrent trip can be estimated using: v oc = 100 v oc i rev r sw 15 ? ? ? ? ? ? 2 + v rev 15 ? ? ? ? ? ? 2 if the above error is greater than 30%, then the v oc thresh- old may need to be increased accordingly. to ensure that the inductor doesnt saturate prior to the sg over current t rip, the inductor should have a saturation current such that: i lsat > v oc(max) r ds(min) where v oc(max) is the maximum overcurrent trip based on the above error and r ds(min) is the minimum r ds(on) of the sg mosfet over temperature. while the circuit of figure 30 can be used whenever the sw node plateau voltage is 40v or less, care must be taken to limit the current into the 50v clamp on the sw pin due to overshoot and ringing. figure 31 illustrates a typical sw node waveform. + + ? sgoc 3766 f32 ltc3766 sw r3 r2 main xfmr v out v sw sg v ds(oc) + ? sg mosfet gnd 50v i rev = lv: 103a hv: 42a v rev = lv: 73mv hv: 148mv c r1 ? ? figure 32. sg overcurrent for high v out applications the overshoot and ringing on the sw node is due to the leakage inductance of main transformer, and it is worse at full load and maximum v in . the peak sw node voltage (v sw(pk) ) also depends heavily on the gate drive timing as well as the rc snubber that is typically used on the sw node. see delay resistor selection: pg turn-on transition and rc snubber sections for details. make sure that the peak sw node voltage does not cause more than 0.2a to flow into the sw pin: v sw(pk) ? 50v r sw < 0.2a the above condition is normally satisfied with reasonable values for r sw and the use of an rc snubber to limit v sw(pk) . in applications where the sw node plateau voltage is greater than 40v, it is necessary to add a divider as shown in figure 32. + + ? sgoc 3766 f30 ltc3766 sw r sw main xfmr v out v sw sg v oc + ? sg mosfet gnd 50v i rev = lv: 103a hv: 42a v rev = lv: 73mv hv: 148mv c ? ? figure 30. sg overcurrent for low v out applications 0v v sw(pk) pg sw node 0v 3766 f31 v in n s n p figure 31. typical sw node waveform ltc3766 3766fa
45 for more information www.linear.com/ltc3766 a pplica t ions i n f or m a t ion for the circuit of figure 32, the overcurrent v ds on the sg mosfet is given by: v oc = v rev r1 + r2 r2 ? ? ? ? ? ? ?i rev r1 + r3 r1 + r2 r2 ? ? ? ? ? ? ? ? ? ? ? ? in addition to producing the desired v oc threshold, there are three constraints on the selection of resistors r1, r2 and r3 that must be simultaneously met: 1) r1 and r2 must divide the maximum v sw plateau voltage down to 40v or less, 2) the impedance at the sw pin must be kept as low as possible to reduce the delay in sensing the v sw voltage, and 3) the power dissipation in r1 and r2 must be kept reasonably low. the last two constraints can be met by choosing a maximum power (p r ) to be dissipated in the sum of r1 and r2. typically, setting p r = 0.25w is a reasonable compromise that keeps the time constant low while not greatly impacting converter efficiency. the selection of r1, r2 and r3 is made using the follow - ing procedure: 1. calculate r1 and r2 based on a maximum power (p r = 0.25w) and a divider ratio that will produce exactly 40v maximum on the sw pin: r1 = n s n p v out v in(max) p r ? ? ? ? ? ? ? 40v out p r r2 = 40 ? r1 n s n p v in ? 40 2. if the value for v oc calculated using r1 and r2 from step 1) is greater than the target v oc value, then choose r3 such that i rev ? r3(r1+ r2)/r2 equals the difference between the calculated and target v oc values. 3. if the value for v oc calculated using r1 and r2 from step 1) is less than the target value, then r3 = 0. re - calculate r1 and r2 based on maximum power (p r = 0.25w) and the desired target v oc value: r1 = bi rev ? av oc + av oc + bi rev ( ) 2 ? 4abv rev i rev 2ai rev r2 = b ? ar1 a where a = p r (n p /n s ) and b = v out v in(max) . for the circuit of figure 32, the % error in the sg overcurrent trip can be estimated using: v oc = 100 v oc i rev r1 + k ? r3 ( ) 6 ? ? ? ? ? ? 2 + k v rev 14 ? ? ? ? ? ? 2 where k = (r1 + r2)/r2. rc snubbers most applications will make use of an rc snubber to reduce the overshoot and ringing on the sw and swb pins, as shown in figure 33. the snubber capacitor is chosen to limit the peak voltage overshoot on sw or swb by absorbing the energy in the leakage inductance of the main transformer. the snubber resistor is then chosen to provide optimum damping so as to minimize ringing. a larger snubber capacitor reduces the overshoot, but at the expense of increased power dissipation in the snubber resistor. in general, the snubber on the swb node has far less energy to absorb and can therefore be smaller than that on the sw node. in some cases, the snubber on swb can be eliminated entirely. the precise values needed for the rc snubbers will depend upon the specifics of each application, and should be optimized in the lab. typical values for c s1 and c s2 range from 1nf to 4.7nf, and r s1 and r s2 are typically 1 to 50. always use a high quality ceramic (x7r) capacitor and resistors with a high power rating (1/4w to 1/2w) for and an rc snubber. r s2 r s1 3766 f33 v swb v sw c s2 c s1 v out n s n p main xfmr ?? figure 33. using rc snubbers ltc3766 3766fa
46 for more information www.linear.com/ltc3766 a pplica t ions i n f or m a t ion remote sensing the ltc3766 contains a precision differential amplifier for use in remote sensing applications. as shown in figure 14a, this is useful in eliminating the voltage drops associated with bussing the power supply output voltage to a remote load. be aware that the differential amplifier is powered from the v in pin of the ltc3766, and requires 1.5v of overhead on v in above the output voltage (v sout ). if the voltage on the v in pin is not adequate to support the v sout voltage, the ltc3766 will generate a fault. this is neces - sary to avoid a potential overvoltage on the main output of the converter . in addition, the l tc3766 will generate a fault if the polarity of the v s + and v s C pins are reversed by approximately 0.3v or more. in rare applications, it may be useful to raise the common mode voltage of the v s + and v s C inputs. when doing so, always ensure that v s + < 2(v in C 2v) to prevent saturating the input stage of the differential amplifier. if the input stage is saturated, the ltc3766 forces the v sout pin to 0v. in applications where the differential amplifier is not needed, connect the inputs as shown in either figure?14b or figure 15. self-starting polyphase applications figure 34 shows the polyphase connections for the ltc3765 and ltc3766. on the primary side, the design of one phase of the ltc3765 can be optimized and then replicated up to four times by simply tying the ssflt pins together. the common ssflt pins are held low until all phases have adequate voltage on their v cc supplies and run pins. this prevents any of the phases from switching until every phase has satisfied the requirements for start- up. when start-up conditions have been met, the ssflt pin is released and quickly charged until all phases have in + ? ? ndrv run v cc ssflt c ssp c vcc r fsp r fss r1 v in + v in ? r2 in ? fs/uv ltc3765 ltc3766 (master) gnd ndrv gnd v in v bias phase 1 (master) v cc fb v out + v out ? pt + ss ith pt ? fs/sync c sss in + ? ? ndrv run v cc ssflt c ssp c vcc r fsp r1 v in + v in ? r2 in ? fs/uv ltc3765 ltc3766 (slave) gnd ndrv gnd v in v bias phase 2 (slave) v cc fb v out ? 3766 f34 c sss pt + fs/sync v s ? v s + v sout ith ss pt ? phase figure 34. polyphase connections ltc3766 3766fa
47 for more information www.linear.com/ltc3766 a pplica t ions i n f or m a t ion switched once. the ssflt pin currents then decrease to their nominal values. this ensures that all phases begin their asynchronous, open-loop start-up at nearly the same time. on the secondary side, the ss pins from all phases are interconnected as well. this prevents any one phase from starting until all phases have adequate bias voltage and have detected switching on their respective sw pins. once this condition is met, the master will advance the soft-start voltage to match the v out of the converter, and switching begins on the secondary side on all phases. after a brief lock sequence, all phases will transfer control to the secondary. the ith pins are interconnected between the phases so that current is shared evenly between the master (which controls the ith pin to regulate v out ) and the slaves. the ltc3765 ssflt connection is also used to com - municate faults. if one phase has a primary-side fault (undervoltage, over current, overtemperature, or com - munication loss), it immediately stops switching and rapidly pulls ssfl t to 6v . the other phases will detect that ssflt is above 5v and will also stop switching. on the secondary side, the ltc3766s detect that switching has stopped and also fault, which is communicated to all phases through the common ss connection. the voltage on the primary-side ssflt node then slowly decreases and a restart begins. likewise, if a fault originates on the secondary side on a give phase, this fault is communicated to the other ltc3766s so that all phases stop switching. this will cause a communication fault on the primary side followed by a restart attempt. for the ltc3765 on the primary side, choose components based on a single-phase design. duplicate the single phase to the desired number of phases, up to the maximum of four, with the following modifications: 1. connect the ssflt pins together . instead of having multiple capacitors from the ssflt node to ground, the capacitors can be consolidated into one capacitor with a value equal to n ? c ssflt , where n is the number of phases. 2. if desired, the phases can share the linear regulator of one phase by shorting their v cc and ndrv pins to the linear regulator output; however, be aware that the linear regulator pass device will be dissipating more power and may require a larger and more thermally conduc - tive package. the design and pcb layout are generally simplified if each phase uses its own linear regulator . the secondar y side follows a similar procedure; however, there is more differentiation between the master phase and the slave phases. for the master, choose components based on the above design equations. be aware that each phase should have its own linear regulator pass device to distribute the power dissipation. duplicate the components for each slave, with the following exceptions: 1. connect all of the ss pins together. instead of having multiple capacitors from the ss node to ground, the capacitors can be consolidated into one capacitor . note that only the master charges and discharges the soft- start capacitor. 2. connect the fb pin of the slaves to v cc . this connection puts the ltc3766 into slave mode. in this mode, the ith pin becomes a high impedance input and the ss pin is only used for fault communication. an ltc3766 slave will not perform a pre-set of the soft-start capacitor, nor will it charge or discharge it. a slave can only force the ss pin high to indicate a fault, and it also monitors the ss pin to respond to a fault in another phase. 3. for each slave, the integrated unity-gain differential amplifier is used to sense the voltage on the ith pin of the master. connect the v s + /v s C inputs of each slave between the ith and signal gnd pins of the master. connect the v sout pin on each slave to its own ith pin. 4. connect the fs/sync pins of each slave to the pt C pin of the master. the pt C pin of the master contains the clock signal used to synchronize the slaves and master together. for each slave, set the relative phase using the phase pin. note that ripple current in the input capacitor is minimized by operating the controllers out of phase. for a 2-phase system, set the slave at 180. for a 3-phase system, set the slaves at 120 and 240. for a 4-phase system, set the slaves at 90, 180, and 270. refer to setting the switching frequency and synchronization for details on setting the phase pin. ltc3766 3766fa
48 for more information www.linear.com/ltc3766 a pplica t ions i n f or m a t ion volt-second clamp when used in applications with the ltc3765, direct flux limit will guarantee that no saturation occurs on the main transformer. consequently, there is no need to use a volt- second clamp in applications that have the direct flux limit feature. in applications where the ltc3766 is used standalone, however, the volt-second clamp can be used as a failsafe to prevent excessive volt-seconds from being applied to the main transformer during the pwm on-time. figure 35 illustrates the use of the volt-second clamp. as shown in figure 35, the sw voltage is used to monitor the voltage applied to the main transformer. during the pwm on-time, the c vs capacitor is charged by the sw node through the r vs resistor. for capacitor c vs , use a 5% or better npo-type ceramic capacitor, since accuracy is important. typically a value of 1nf is suitable. likewise, use a 1% resistor for r vs . in high output voltage applications where the sw node must be divided down, use the circuit of figure 36 to set the volt-second clamp. sw sw main xfmr r vs n s n p c vs 3766 f35 ltc3766 v sec ?? figure 35. using the volt-second clamp sw sw main xfmr r vs n s n p c vs 3766 f36 ltc3766 v sec r2 r1 ?? figure 36. volt-second clamp in high v out application sg r vin (for v in > 30v) v in v cc v aux ndrv pt + v out regsd lv bias supply mode pg swp swb main xfmr sw v in c rst c rsd c vaux ltc3766 fg c vin 5v to 15v q p c vcc 3766 f37 ?? figure 37. nonisolated resonant-reset application the pwm on-time is terminated when a pre-determined threshold is reached. this will limit the applied volt-second product to: (v ? s) lim = 0.605r vs c vs the above equation is accurate even when the peak volt - age on the sw node is relatively low and the charging is nonlinear , such as in low v out applications. this is possible because the ltc3766 senses the voltage on the sw pin and adjusts the internal volt-second comparator reference so that constant volt-seconds are maintained regardless of the voltage on sw. consequently, it is important that the ltc3766 sw pin be connected to the secondary sw node for proper sensing of this voltage to occur. the volt-second limit should normally be set approximately 10% above the operational volt-second requirement. to accomplish this, calculate r vs using: r vs = 1.10 v out 0.605f sw c vs in this case, assuming r vs >> r1||r2, r vs can be calcu - lated using: r vs = 1.10 v out 0.605f sw c vs r2 r1 + r2 ? ? ? ? ? ? nonisolated applications in addition to being used with the ltc3765 in isolated applications, the ltc3766 can also be used standalone to make a nonisolated resonant-reset forward converter as shown in figure 37. in this application, the primary-side mosfet is driven directly by the pt + pin, and the mode ltc3766 3766fa
49 for more information www.linear.com/ltc3766 a pplica t ions i n f or m a t ion run r1 r2 run/stop control ltc3766 v in gnd 3766 f38 figure 38. run/stop control for standalone applications pin is tied to gnd through either a 100k or 50k resistor to select lv or hv operating mode. the bias for the v in pin is normally taken directly from the input voltage of the converter. the ltc3766 contains a current-limited internal 30v shunt to simplify applications where v in > 30v. in such applications, place a current limiting resistor in series with the v in pin calculated using: r vin = v in(max) ? 30v 3.5ma note that at low v in , there will be a maximum drop across r vin equal to (1.2ma) ? (r vin ) that is due to the v in pin operating current. for proper operation, the voltage on the v in pin at low input voltage must be greater than the rising v cc uvlo by at least the threshold voltage of q p . using a mosfet for q p instead of an npn eliminates the base current that would otherwise add to the v in operating current. if more margin is needed at low v in operation, a darlington transistor is another option for q p . to reduce power dissipation in q p , a low voltage bias sup - ply should be fed into the v aux pin to power the bypass ldo. this bias supply can be generated off of either the primary or secondary of the main transformer using an auxiliary buck or an inductor overwinding supply. during an output overload condition, the low voltage bias supply will collapse, causing the high voltage linear regulator controller to be re-energized. to prevent excessive power dissipation under this condition, place a capacitor on the regsd pin to limit the operating time of the high voltage linear regulator. the run pin can be used as an undervoltage lockout (uvlo) on the converter input voltage. direct run/stop control can be achieved by using a small nmos on the run pin as shown in figure 38. the resonant reset capacitor, c rst , serves to generate a voltage on the swp node during the off-time of the primary mosfet that resets the transformer flux on a cycle-by-cycle basis. this capacitor is normally sized so that the swp voltage exactly resonates back to v in at the end of the off time with minimum v in : c rst 1 l m 1 f sw 1? v out v in(min) n p n s ? ? ? ? ? ? ? ? ? ? ? ? ? ? 2 ? c par where l m is the main transformer magnetizing inductance and c par is the total parasitic capacitance on swp: c par = c oss(pg) + n s n p ? ? ? ? ? ? 2 c oss(fg) + c snub ( ) c par includes the drain capacitance of both the pg and fg mosfets as well as any snubber capacitance on the swb node. in reality, the presence of leakage inductance makes the swp node rise much faster than it otherwise would. as a result, the optimum value for c rst can be 40% to 60% higher than that calculated by the above equation. the steady-state peak voltage on the primary and forward mosfets is given by: v ds(pg) = v in(max) + v out 2f sw n p n s 1 l m c rst + c par ( ) v ds(fg) = v out 2f sw 1 l m c rst + c par ( ) if a larger value of c rst is used, the peak voltage stresses can be decreased, possibly allowing the use of a mosfet with lower bv dss rating. however, with a larger c rst the swp voltage at low v in will not have time to resonate back down to v in , thereby increasing the turn-on switching losses. in practice, some truncation of the low v in reset waveform is often tolerated to maximize the overall effi - ciency of the converter. note also that the peak mosfet voltage stress during transients can be considerably higher , so allow at least 30% margin above these calculated volt - ages. the volt-second clamp can be used to reduce the peak voltage stress due to load transients. ltc3766 3766fa
50 for more information www.linear.com/ltc3766 a pplica t ions i n f or m a t ion the setting of the gate drive timing for a resonant reset converter is simplified by the adaptive delays featured in the ltc3766. when standalone mode is active (100k or 50k on mode), the fgd pin is ignored, and the associated dead time between sg turn-off and pg turn-on is controlled adaptively. in this mode, ltc3766 delays the pg turn-on until after the sg pin has fallen below approximately 0.5v. for the pg turn-off transition, the sgd resistor is chosen to minimize the dead time and also prevent collapse of the swp node (i.e., catch the swp voltage at its peak if possible). note that setting the fg turn-off so as to catch the swp voltage near its peak will improve efficiency and allow for the use of a larger resonant reset capacitor, thereby reducing the peak voltage stresses on the mosfets. adaptive delay limiting on this edge ensures that sg will not go high until sw has fallen, so shoot-through is not a concern. in nonisolated applications, the inductor current is normally sensed on the input side of the power transformer, typi - cally using a sense resistor. note that in this situation, the values for the sense resistor (r sense ) and the i pk resistor (r ipk ) should be calculated using the above equations, but then scaled by a factor of np/ns. for applications where the transformer is configured to step up the volt - age, however, it may be more efficient to sense current on the output side of the power transformer. in this case, be careful to avoid transformer saturation by keeping the resonant reset capacitor as small as possible and making use of the volt-second clamp. common mode noise common mode noise arises in isolated converter applica - tions due to the parasitic capacitance between the primary and secondar y windings of the main transformer. when rapid voltage changes occur on the primary-side mosfet drain, this will inject current through the inter-winding capacitance. this causes the ground reference of the secondary to suddenly jump with respect to the primary ground. as a result, current is injected across the inter- winding capacitance of the pulse transformer back to the primary, and a resulting common mode voltage can appear at the in + and in C inputs of the ltc3765. while the ltc3765 has been carefully designed to reject this common mode voltage, always use a common mode filter capacitor that is directly connected between the primary and secondary grounds. this capacitor shunts away the common mode noise. typically, a value of 2.2nf is adequate. use a high quality ceramic y capacitor rated for 250vac operation, or other voltage rating as needed for the isolation and safety requirements of the particular application. thermal considerations when designing a forward converter with an output power of 50w or more, particular attention must be paid to the thermal aspects of the design and layout. in general, it is better to use multiple elements in parallel to spread out the power dissipation and reduce temperature rise. beneath all power mosfets, use thermal vias and copper islands on multiple layers to provide cooling. if excessive temperature rise occurs, both the ltc3765 and the ltc3766 contain overtemperature shutdown circuits that will help to prevent thermal damage. both overtemperature shutdowns are set at approximately 165c rising with 20c of hysteresis. pcb checklist the ltc3766 requires proper bypassing on the v cc supply due to its high speed switching (nanoseconds) and large ac currents (amperes). careless component placement and pcb trace routing may cause excessive ringing and undershoot/overshoot. to obtain optimum performance from the ltc3766: 1. use a low inductance, low impedance ground planes to reduce any ground drop and stray capacitance. remember that the ltc3766 switches at greater than 2a peak currents and the power mosfet s can carry 50a or more. any significant ground drop will degrade signal integrity. ltc3766 3766fa
51 for more information www.linear.com/ltc3766 a pplica t ions i n f or m a t ion 2. plan the power/ground routing carefully. know where the large load switching current is coming from and going to. maintain three separate planes if possible: signal ground (gnd pin), power ground (pgnd pin) and power stage ground. the power ground plane should be connected with a single via to the source of the sg mosfet. the signal ground plane should be connected with a single via to the source of the sg mosfet for accurate v ds sensing. if resistor current sensing is used for i s + and i s C , be careful to minimize the inductance of the plane between the sense resistor and the source of the sg mosfet. 3. mount a bypass capacitor as close as possible between the v cc pin and the power ground plane. 4. keep the copper traces between the driver output pins and the mosfet short and wide. 5. keep the high current switching path on both the primary and secondary as short as possible, using multiple lay - ers in parallel to further reduce parasitic inductance. 6. if resistor sense mode is used, the i s + and i s C pins must be kelvin connected to the sense resistor. the traces to the sense resistor must run side-by-side and be shielded with signal ground on all sides. 7. keep the switching nodes (sw, pt + , pt C , fg, sg) away from noise sensitive nodes, especially fb, ith, i s + and i s C . 8. the voltage divider on the output should be connected as close as possible to the load at the output terminal of the power supply. the bottom of the voltage divider should be tied to the signal ground plane. use the dif - ferential amplifier to sense the load voltage and eliminate distribution voltage drops. ltc3766 3766fa
52 for more information www.linear.com/ltc3766 figure 39. 36v-72v to 5v/15a active clamp isolated forward converter typical a pplica t ions fg i s ? i s + pt + fb ith pt ? ss sw sg gnd pgnd sgd fgd mode run v in ndrv ltc3766 v cc run si3437dv (sot23) 15m 1/2w 3m 2w v cc in + in ? fs/uv ssflt ndrv pg r core delay sgnd 14k 18.2k l1: pulse pa1392.152 t1: pulse pa0810 t2: pulse pa0297 15k 26.1k 100 100 100 33nf npo 22.1k 17.8k 3766 ta02 604 4.42k 0.1f t2 2:1 t1 6:2 10.5k 15.0k 365k i pk v sec 200k si3440dv ?v in +v in 36v to 72v fdms86201 bsc0901ns ?? sir414dp 33nf 4.7f ltc3765 pgnd i s + i s ? ag 1 168 i smag fs/sync v s + v s ? 330pf 1.0f 2.2nf 250v 33nf 200v 47pf 220pf 470pf 2.2f 100v 3 220f 6.3v 2 l1 1.4h +v out 5v 15a ?v out 1nf 100v 10 1/4w 1f 10v 100nf 200v ? ? load step efficiency vs load current pre-biased start-up load current (a) 3 86 efficiency (%) 88 90 92 94 96 5 7 9 11 3766 f39b 13 15 v in = 36v v in = 48v v in = 72v v out 1v/div i l1 5a/div 200s/div 3766 f39c v in = 48v v prebias = 4.6v v out 200mv/div i out 5a/div 20s/div 3766 f39d v in = 48v v out = 5v load step = 5a to 15a ltc3766 3766fa
53 for more information www.linear.com/ltc3766 typical a pplica t ions 9v-36v to 24v/4.2a active clamp isolated forward converter sgnd pgnd gnd pgnd ltc3766 sw sg i s ? i s + run 1nf 220pf 68pf 1f d1 +v in ?v in 33nf 27.4k 100 14.3k 147k 28.7k 100f 35v: suncon 35hvh100m d1-d2: zhcs506 d3-d6: bas21 l1: vishay ihlp2525czerr47m01 l2: pulse pa2729.583 l3: cooper sd25-681 q1: bsc057n08ns3 q2: si7430dp q3: bsc320n20ns3g t1: pulse pa0806.004nl t2: pulse pa0510nl t3: ice ct102-100 (1:100) ssflt 15k 60.4k 7.5k 274 81.6k 15k 16.9k 2.94k 3766 ta03a 10.7k rcore fs/uv 6.19k 10k si7309dn q1 1f 100v 10f 50v 3 10f 50v 0.33 1/8w 3.65 delay in ? v cc pt + fb regsd mode ss i s ? pt ? fgd sgd fs/sync i pk ith v sec phase v s ? v s + run in + ndrv 2n7002 ag pg 100 es1pd 100 100 4m 1w 15 1/8w 150pf 250v 24 1w 220nf 100v t1 t3 d3 i s + +v in 9v to 36v 1.2k 1/8w l1 0.47h 8t 4t d4 d5 q2 q3 +v out 24v 4.2a +v out ?v out +v out 2t ismag +v in 2.2nf 250vac 3.3nf 0.1f t2 2.5:2 1nf d2 1f 0.1f 3.3nf i s + i s + v cc v aux ndrv fg v in 4.7f 2.2f l3 680h 33nf npo 2.2nf ltc3765 0.1f 100k 1nf 100f 35v ? ? ? ? ? ?? l2 58h 10f 50v d6 7.5k 1/2w 2.8k 1/8w + fcx491a ltc3766 3766fa
54 for more information www.linear.com/ltc3766 18v-75v to 12v/12.5a active clamp isolated forward converter typical a pplica t ions efficiency vs load current sgnd pgnd gnd pgnd ltc3766 sw sg i s ? i s + run 10nf 220pf 47pf 1f d1 +v in ?v in 33nf 27.4k 100 13.3k 61.9k 4.99k 68f 16v: sanyo 16tqc68m d1-d2: zhcs506 d3: bas21 l1: vishay ihlp4040dzer1r8m11 l2: pulse pa2729.113nl q1: fdms86201 q2: bsc057n08ns3 q3: bsc190n15ns3 t1: pulse pa0801 t2: pulse pa0510nl t3: ice ct102-100 (1:100) ssflt 15k 60.4k 1.82k 604 75k 10k 16.9k 1.87k 3766 ta04a 11.5k rcore fs/uv 6.19k 10k irf6217 q1 0.22f 250v 2.2f 100v 3 2.2f 100v 0.75 1/8w 5.11 1/8w delay in ? v cc pt + fb mode ss i s ? pt ? fgd sgd fs/sync i pk ith v sec phase regsd v s ? v s + run in + ndrv fdc2512 ag pg 100 es1pd 100 100 4m 1w 75 1/8w 33nf 200v t1 t3 d3 i s + +v in 18v to 75v 1.2k 1/8w l1 1.8h 4t q2 q3 +v out 12v 12.5a ?v out +v out +v out 4t ismag +v in 2.2nf 250vac 10nf 0.1f t2 2.5:2 1nf d2 1f 3.3nf i s + v cc ndrv fg v in 10f 33nf npo i s + 1nf ltc3767 0.1f 200k 1nf 68f 16v 2 ?? ? ? ?? l2 11h es1pd 22f 16v 2 1.82k 1/4w 33k 1/2w 1.82k 1/4w + fmmt491 1nf 200v 51 1/2w 100pf 200v load current (a) 0 efficiency (%) 92 94 96 12 3766 ta04b 90 88 86 3 6 9 15 v in = 24v v in = 48v ltc3766 3766fa
55 for more information www.linear.com/ltc3766 typical a pplica t ions 36v-60v to 32v at 10a 320w isolated p/a power supply sgnd pgnd gnd pgnd ltc3766 sw sg i s ? i s + run 10nf 220pf 100pf 1f d1 +v in ?v in 33nf 27.4k 100 8.25k 66.5k 2.43k 56f 50v: suncon 50hv56m d1-d2: zhcs506 d3-d6: bas21 l1: vishay ihlp6060dzer1r8m11 l2: coilcraft ser2814h-103 l3: cooper sd25-681 q1-q6: bsc190n15ns3 t1: pulse pa0905nl t2: pulse pa0510nl t3: ice ct102-100 (1:100) ssflt 15.0k 60.4k 8.66k 1.54m 604 205k 33.2k 47k 27.4k 3.09k 3766 ta05a 31.6k 1k rcore fs/uv 13k 10k irf6217 q1 q2 0.22f 250v 2.2f 100v 3 2.2f 100v 0.56 1/8w 4.22 delay in ? v cc pt + fb regsd mode ss i s ? pt ? fgd sgd fs/sync i pk ith v sec phase v s ? v s + run in + ndrv fdc2512 ag pg 100 es1pd 100 100 4m 1w 165 1/8w 33nf 200v t1 t3 d6 i s + +v in 36v to 60v 330 1/8w l1 1.8h 6t 2t d4 d3 d5 q3 q4 q5 q6 +v out 32v 10a ?v out +v out +v out 4t ismag +v in 2.2nf 250vac 2.2nf 0.1f t2 2.5:2 1nf d2 1f 0.1f 3.3nf i s + i s + v cc v aux ndrv fg v in 1f 3.9v 4.7f l3 680h 33nf npo 1.5nf ltc3765 0.1f 200k 1nf ? ? ? ? ? ?? l2 10h 4.7f 50v 4 0.1f 50v 56f 50v 2 8.66k 1/8w 2.94k + fcx491a 330pf efficiency vs load current load current (a) 2 efficiency (%) 93 94 10 3766 ta05b 92 91 4 6 8 96 v in = 48v 95 ltc3766 3766fa
56 for more information www.linear.com/ltc3766 36v-60v to 14v at 25a 350w isolated bus converter typical a pplica t ions efficiency vs load current sgnd pgnd gnd pgnd ltc3766 sw sg i s ? i s + run 10nf 220pf 100pf 1f d1 +v in ?v in 33nf 27.4k 100 11k 66.5k 2.43k 68f 16v: sanyo 16tqc68m d1-d2: zhcs506 d5: bas21 l1: vishay ihlp4040dzer1r8m11 l2: coilcraft ser2814l-472kl q1-q3: bsc190n15ns3 q4-q7: bsc057n08ns3 t1: pulse pa0956nl t2: pulse pa0510nl t3: ice ct102-100 (1:100) ssflt 15.0k 60.4k 604 150k 10k 27.4k 3766 ta06a 13.7k rcore fs/uv 14k 10k irf6217 q1 q2 q3 0.22f 250v 2.2f 100v 3 2.2f 100v 0.68 1/8w 4.22 432 1/8w delay in ? v cc pt + fb mode ss i s ? pt ? fgd sgd fs/sync i pk ith v sec phase v s ? regsd v s + run in + ndrv fdc2512 ag pg 100 es1pd 100 100 4m 1w 165 1/8w 1.00k 1/8w 33nf 200v t1 t3 i s + +v in 36v to 60v l1 1.8h 3t q4 q5 q6 q7 10nf 200v +v out 14v 25a ?v out +v out +v out 5t ismag +v in 2.2nf 250vac 4.7nf 0.1f t2 2.5:2 1nf d2 1f 3.3nf i s + d5 v cc ndrv fg v in 4.7f 33nf npo i s + 1nf ltc3767 0.1f 200k 1nf 68f 16v 4 22f 16v 4 ?? ? ? ?? l2 4.7h es1pd 5.1k 1w + fcx491a load current (a) 0 91 efficiency (%) 92 93 94 95 96 5 10 15 20 3766 ta06b 25 30 v in = 48v ltc3766 3766fa
57 for more information www.linear.com/ltc3766 p ackage descrip t ion .386 ? .393* (9.804 ? 9.982) gn28 rev b 0212 1 2 3 4 5 6 7 8 9 10 11 12 .229 ? .244 (5.817 ? 6.198) .150 ? .157** (3.810 ? 3.988) 202122232425262728 19 18 17 13 14 16 15 .016 ? .050 (0.406 ? 1.270) .015 .004 (0.38 0.10) 45 0 ? 8 typ .0075 ? .0098 (0.19 ? 0.25) .0532 ? .0688 (1.35 ? 1.75) .008 ? .012 (0.203 ? 0.305) typ .004 ? .0098 (0.102 ? 0.249) .0250 (0.635) bsc .033 (0.838) ref .254 min recommended solder pad layout .150 ? .165 .0250 bsc .0165 .0015 .045 .005 * dimension does not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side ** dimension does not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side inches (millimeters) note: 1. controlling dimension: inches 2. dimensions are in 3. drawing not to scale 4. pin 1 can be bevel edge or a dimple gn package 28-lead plastic ssop (narrow .150 inch) (reference ltc dwg # 05-08-1641 rev b) ltc3766 3766fa
58 for more information www.linear.com/ltc3766 p ackage descrip t ion 4.00 0.10 (2 sides) 2.50 ref 5.00 0.10 (2 sides) note: 1. drawing proposed to be made a jedec package outline mo-220 variation (wxxx-x). 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 top mark (note 6) 0.40 0.10 27 28 1 2 bottom view?exposed pad 3.50 ref 0.75 0.05 r = 0.115 typ r = 0.05 typ pin 1 notch r = 0.20 or 0.35 45 chamfer 0.25 0.05 0.50 bsc 0.200 ref 0.00 ? 0.05 (ufd28) qfn 0506 rev b recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 0.70 0.05 0.25 0.05 0.50 bsc 2.50 ref 3.50 ref 4.10 0.05 5.50 0.05 2.65 0.05 3.10 0.05 4.50 0.05 package outline 2.65 0.10 3.65 0.10 3.65 0.05 ufd package 28-lead plastic qfn (4mm 5mm) (reference ltc dwg # 05-08-1712 rev b) ltc3766 3766fa
59 for more information www.linear.com/ltc3766 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa - tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. r evision h is t ory rev date description page number a 6/13 switch polarity between i s + and i s C in figure 11 28 ltc3766 3766fa
60 for more information www.linear.com/ltc3766 ? linear technology corporation 2011 lt 0613 rev a ? printed in usa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com/ltc3766 r ela t e d p ar t s typical a pplica t ion part number description comments ltc3765 active clamp forward controller and gate driver direct flux limit, supports self-starting secondary forward control, works in conjuction with ltc3766 ltc3705/ltc3726 2-switch synchronous forward no opto isolated controller chip set self-starting architecture eliminates need for bias voltage on primary side lt ? 1952/lt1952-1 isolated synchronous forward active clamp contollers suitable for medium power 12v, 24v and 48v input applications, adjustable synchronous rectification timing ltc3723/ltc3723-2 synchronous push-pull and full-bridge controllers high efficiency with on-chip mosfet drivers, adjustable synchronous rectification timing ltc3721-1/ltc3721-2 nonsynchronous push-pull and full-bridge controllers minimizes external components, on-chip mosfet drivers ltc3722/ltc3722-2 synchronous isolated full-bridge controllers adaptive or manual delay control for zero voltage switching, adjustable synchronous rectification timing 36v-72v to 3.3v/20a nonisolated resonant-reset forward converter + si2328ds (sot23) bsc320n20ns3 ndrv fs/sync ith ss i s ? i s + pt + v aux fg sw sg 33nf 1f 16v 0.1f 50v 1nf v cc v in run v sout fb v s ? v s + regsd 0.22f 1.5nf 200v npo v in 36v to 72v 47pf 2.2nf ?sense +sense 8.62k 16.2k 16.5k 1/4w 100 15m 1w 100 l2 1mh l1 0.85h 2.4 1/4w l1: pulse pa1294.910nl l2: cooper sd25-102 t1: pulse pa0810.006nl 1nf 50v 210k 7.87k gnd pgnd ltc3766 330pf v sec sgd 49.9k mode 20.5k 6.2k 1.82k 100 3766 ta07 100 i pk 2.2f 100v 3 1f 12t 6t 2t t1 bat54 bat54 bsc0901ns bsc0901ns v out 3.3v 20a 220f 6.3v 100f 6.3v 2 ? ? ? load step efficiency vs load current start-up load current (a) 6 86 efficiency (%) 88 90 92 94 8 10 12 14 3766 ta07b 16 18 20 v in = 36v v in = 48v v in = 72v v out 1v/div i l 5a/div 1ms/div 3766 ta07c v in = 48v v out = 3.3v r load = 0.22 v out 200mv/div i out 5a/div 20s/div 3766 ta07d v in = 48v v out = 3.3v load step = 10a to 20a ltc3766 3766fa

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